CN101116382A - 陶瓷多层基板及其制造方法 - Google Patents
陶瓷多层基板及其制造方法 Download PDFInfo
- Publication number
- CN101116382A CN101116382A CNA2006800040962A CN200680004096A CN101116382A CN 101116382 A CN101116382 A CN 101116382A CN A2006800040962 A CNA2006800040962 A CN A2006800040962A CN 200680004096 A CN200680004096 A CN 200680004096A CN 101116382 A CN101116382 A CN 101116382A
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- Prior art keywords
- main body
- installation component
- multilayer board
- silicone film
- board main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000919 ceramic Substances 0.000 title claims abstract description 159
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 239000003566 sealing material Substances 0.000 claims abstract description 85
- 229920006268 silicone film Polymers 0.000 claims description 159
- 238000009434 installation Methods 0.000 claims description 145
- 238000003466 welding Methods 0.000 claims description 123
- 239000000758 substrate Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 34
- 238000005516 engineering process Methods 0.000 claims description 32
- 239000008393 encapsulating agent Substances 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 2
- 229920005989 resin Polymers 0.000 abstract description 36
- 239000011347 resin Substances 0.000 abstract description 36
- 230000005012 migration Effects 0.000 abstract description 14
- 238000013508 migration Methods 0.000 abstract description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000007789 sealing Methods 0.000 abstract description 9
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 abstract description 3
- -1 siloxanes Chemical class 0.000 description 21
- 238000005240 physical vapour deposition Methods 0.000 description 18
- 238000005987 sulfurization reaction Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 230000007613 environmental effect Effects 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 5
- 239000003292 glue Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 238000010504 bond cleavage reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 230000003301 hydrolyzing effect Effects 0.000 description 3
- 230000007017 scission Effects 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 238000009736 wetting Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- 239000011812 mixed powder Substances 0.000 description 2
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910052946 acanthite Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000004087 circulation Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002068 genetic effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000037 hydrogen sulfide Inorganic materials 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- XUARKZBEFFVFRG-UHFFFAOYSA-N silver sulfide Chemical compound [S-2].[Ag+].[Ag+] XUARKZBEFFVFRG-UHFFFAOYSA-N 0.000 description 1
- 229940056910 silver sulfide Drugs 0.000 description 1
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- H—ELECTRICITY
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- H05K3/46—Manufacturing multilayer circuits
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Abstract
提供了具有极好的抗迁移性以及在树脂密封材料与陶瓷多层基板主体之间的高接合强度的陶瓷多层基板,及这种陶瓷多层基板的制造方法。用通过PVD方法形成的硅氧烷膜完全覆盖包括焊区(16,17)和外部电极(24,25)的多层基板主体(2)。将硅氧烷膜的厚度设置为低于100nm。然后,安装组件(11)的外部电极(13,14)通过焊料(19)电连接到多层板主体(2)的焊区(16,17)并固定。然后,在多层基板主体(2)上形成用于密封安装组件(11)的树脂密封材料(4)。
Description
技术领域
本发明涉及陶瓷多层基板及其制造方法,尤其涉及用于在其表面上安装诸如IC组件之类的电子组件的陶瓷多层基板及其制造方法。
背景技术
一般而言,在陶瓷多层基板中,在基板表面上形成用于安装安装组件的基于Ag或Cu的焊区和用于安装多层基板本身的另外的外部电极。在焊区和外部电极上,形成可焊接且可引线接合的电镀膜。电镀膜也具有抑制焊区和外部电极迁移的效果。
然而,以前,当陶瓷多层基板在高电场下使用时,因为在焊区和外部电极上形成的电镀膜不能充分地抑制迁移,所以除电镀膜以外还需要由玻璃或树脂制成的保护膜的形成。因此,由于保护膜的形成,有关于设计限制以及制造成本增加的问题。
此外,如专利文献1所述,为了保护安装在陶瓷多层基板上的安装组件,在某些情况下,用树脂密封材料来密封安装组件。然而,因为树脂密封材料和陶瓷多层基板主体之间的润湿性不好,所以还存在树脂密封材料和陶瓷多层基板主体之间的接合强度不够的问题。
此外,关于通过溅射形成硅氧烷膜的技术,在专利文献2和专利文献3中有描述。
专利文献1:日本未审查专利申请公布第2003-249840号
专利文献2:日本未审查专利申请公布第06-152109号
专利文献3:日本未审查专利申请公布第08-213742号
发明公开
因此,本发明的目的是提供一种具有极好的抗迁移性以及树脂密封材料和陶瓷多层基板主体之间的高接合强度的陶瓷多层基板及其制造方法。
为了实现上述目的,根据第一发明的陶瓷多层基板的特征在于包括通过层叠多个陶瓷层和内部导体层组成的层叠基板主体、设置在层叠基板主体的表面上用于电连接到安装组件的外部电极的焊区;以及被设置成覆盖层叠基板主体和焊区且厚度低于100nm的硅氧烷膜。
此外,关于根据第一发明的陶瓷多层基板,较佳地将硅氧烷膜设置成覆盖经由焊料安装在焊区上的安装组件及焊料的至少一部分。
根据第二发明的陶瓷多层基板的特征在于包括通过层叠多个陶瓷层和内部导体层组成的层叠基板主体;设置在层叠基板主体的表面上用于电连接到安装组件的外部电极的焊区;经由焊料安装在焊区上的安装组件;以及被设置成覆盖层叠基板主体、安装组件和焊料的至少一部分且厚度低于100nm的硅氧烷膜。
此外,关于根据第一和第二发明的陶瓷多层基板,它们较佳地包括用于密封安装组件的树脂密封材料。此外,较佳地用硅氧烷膜覆盖树脂密封材料。
根据第三发明的陶瓷多层基板的特征在于包括通过层叠多个陶瓷层和内部导体层组成的层叠基板主体;设置在层叠基板主体的表面上用于电连接到安装组件的外部电极的焊区;经由焊料安装在焊区上的安装组件;用于密封安装组件的树脂密封材料;以及被设置成覆盖层叠基板主体和树脂密封材料且厚度低于100nm的硅氧烷膜。
在根据第一至第三发明的陶瓷多层基板中,安装组件较佳地包括IC组件并通过引线接合电连接到焊区。IC组件可被包含在设置在层叠基板主体的一个主表面上的空腔中。此外,也可在焊区上形成电镀膜。
根据第四发明的陶瓷多层基板的制造方法的特征在于包括以下步骤:通过层叠多个陶瓷层和内部导体层形成层叠基板主体;在层叠基板主体的表面上形成电连接到安装组件的外部电极的焊区;以及通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖层叠基板主体和焊区。
关于根据第四发明的陶瓷多层基板的制造方法,它们还包括以下步骤:经由焊料在其上形成硅氧烷膜的焊区上安装一安装组件;以及通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖安装组件和焊料的至少一部分。
根据第五发明的陶瓷多层基板的制造方法的特征在于包括以下步骤:通过层叠多个陶瓷层和内部导体层形成层叠基板主体;在层叠基板主体的表面上形成电连接到安装组件的外部电极的焊区;经由焊料将安装组件安装到焊区上;以及通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖安装组件和焊料的至少一部分。
关于根据第四和第五发明的陶瓷多层基板的制造方法,它们可包括在通过PVD工艺形成硅氧烷膜以覆盖安装组件的步骤之后,用树脂密封材料密封安装组件的步骤。此外,它们还可包括在通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖树脂密封材料的步骤。
根据第六发明的陶瓷多层基板的制造方法的特征在于包括以下步骤:通过层叠多个陶瓷层和内部导体层形成层叠基板主体;在层叠基板主体的表面上形成电连接到安装组件的外部电极的焊区;经由焊料将安装组件安装到焊区上;用树脂密封材料密封安装组件;以及通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖层叠基板主体和树脂密封材料。
根据第七发明的陶瓷多层基板的制造方法的特征在于包括以下步骤:通过层叠多个陶瓷层和内部导体层形成层叠基板主体;在层叠基板主体的表面上形成电连接到安装组件的外部电极的焊区;在焊区上形成焊球;通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖焊区和焊球;通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖安装组件;以及经由焊球将安装组件安装到焊区上。
根据第八发明的陶瓷多层基板的制造方法的特征在于包括以下步骤:通过层叠多个陶瓷层和内部导体层形成层叠基板主体;在层叠基板主体的表面上形成电连接到安装组件的外部电极的焊区;在焊区上形成焊球;通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖层叠基板主体和焊区;在安装组件上形成焊球;通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖安装组件和焊球;以及经由焊球将安装组件安装到焊区上。
关于根据第七和第八发明的陶瓷多层基板的制造方法,它们可包括在安装安装组件的步骤之后,用树脂密封材料密封安装组件的步骤。此外,它们还可包括通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖层叠基板主体和树脂密封材料的步骤。
关于根据第四至第八发明的陶瓷多层基板的制造方法,它们较佳地包括活化硅氧烷膜的表面的步骤。活化硅氧烷膜的步骤较佳地通过使硅氧烷膜的表面受到利用氧等离子体的清洗来进行。
发明优点
根据本发明,因为设置了厚度低于100nm的硅氧烷膜以覆盖层叠基板主体和焊区,所以通过防水效应,可改进抗迁移性,并且还改进了诸如硫化和氧化之类的化学环境特性。此外,因为硅氧烷膜的厚度低于100nm,所以可以没有问题地进行焊接和引线接合。
如果层叠基板主体和经由焊料安装的安装组件两者都用硅氧烷膜覆盖,则硅氧烷膜覆盖焊料的暴露部分,从而能够抑制焊料的流出。
此外,当包括用于密封安装组件的树脂密封材料时,树脂密封材料和硅氧烷膜之间的润湿性是良好的,且硅氧烷膜和层叠基板主体之间的接合强度也高,从而能够增强树脂密封材料和层叠基板主体之间的接合强度。
如果设置了树脂密封材料以覆盖硅氧烷膜,则抑制了树脂密封材料的湿气吸收,从而能够抑制由于树脂密封材料吸收的湿气而引起的安装组件的特性改变,或由树脂密封材料的水解导致的杂质。
此外,如果层叠基板主体和树脂密封材料同时用硅氧烷膜覆盖,则层叠基板主体和树脂密封材料之间的界面的侧面用硅氧烷膜覆盖,从而能够抑制层叠基板主体和树脂密封材料之间的界面的剥离。
如果安装组件经由覆盖有硅氧烷膜的焊球安装在基板主体上,则可进一步确定地抑制焊料的流出。
附图简述
图1是示出根据本发明的陶瓷多层基板的第一实施例的截面图。
图2是示出形成硅氧烷膜的步骤的说明性视图。
图3是示出基于硅氧烷的树脂的量与硅氧烷膜的厚度之间的关系的图。
图4是示出基于硅氧烷的树脂的量与润湿的面积之间的关系的图。
图5是示出根据本发明的陶瓷多层基板的第一实施例的修改实施例的横截面图。
图6是示出根据本发明的陶瓷多层基板的第二实施例的横截面图。
图7是示出根据本发明的陶瓷多层基板的第三实施例的横截面图。
图8是示出根据本发明的陶瓷多层基板的第四实施例的横截面图。
图9是示出根据本发明的陶瓷多层基板的第五实施例的横截面图。
图10是示出根据本发明的陶瓷多层基板的第五实施例的修改实施例的横截面图。
图11是示出根据本发明的陶瓷多层基板的第五实施例的另一个修改实施例的横截面图。
图12是示出根据本发明的陶瓷多层基板的第六实施例的横截面图。
图13是示出根据本发明的陶瓷多层基板的第七实施例的横截面图。
图14是示出根据本发明的陶瓷多层基板的第八实施例的横截面图。
图15是示出根据本发明的陶瓷多层基板的第九实施例的横截面图。
本发明的最佳实现方式
在下文中,将参考附图描述根据本发明的陶瓷多层基板及其制造方法的实施例。
第一实施例(参见图1至图4)
图1中所示的陶瓷多层基板1基本由层叠基板主体2、安装在层叠基板主体2上的安装组件(IC组件)11以及用于密封安装组件11的树脂密封材料4组成。
焊区16和17在层叠基板主体2的上表面上形成。安装组件11安装在层叠基板主体2上,设置在安装组件11的底面上的外部电极13和14经由焊料19连接到焊区16和17。
在层叠基板主体2的内部,形成内部导体图案22和23。内部导体图案22的一端和内部导体图案23的一端分别经由形成于层叠基板主体2中的通孔导体20电连接到焊区16和17。内部导体图案22和23的另一端分别电连接到从侧面到达层叠基板主体2的底面的外部电极24和25。
层叠基板主体2通过以下制造工序来制造。首先,将由SiO2、Al2O3、B2O3和CaO制成的结晶玻璃粉末和氧化铝粉末以相等的重量比混和。通过将15份重量的聚乙烯醇缩丁醛、40份重量的异丙醇和20份重量的trole添加到100份重量的混和粉末中,并且在球磨机中混和24小时,制成了一种浆体。通过用刮浆刀工艺使浆体形成120μm厚的板,获得陶瓷印刷电路基板。
接着,在预定的陶瓷印刷电路基板中形成用于通孔的孔。随后,在用于通孔的孔中填充导电胶以形成通孔导体20,并且内部导体图案22和23通过丝网印刷工艺形成于每一个陶瓷印刷电路基板上。此外,在内部导体图案22和23通过丝网印刷工艺形成于每一个陶瓷印刷电路基板上的同时,通孔导体20可通过在用于通孔的孔中填充导电胶来形成。
在层叠后,陶瓷印刷电路基板在50MPa的压力下以及60℃的温度下接触接合以形成层叠块。在将层叠块切成具有预定尺寸的片后,将这些片一次全部烧结。由此,它们形成为低温烧结陶瓷层叠基板主体2。
接着,通过在层叠基板主体2的表面上涂导电胶,以及其随后对其进行烘焙,形成焊区16和17及外部电极24和25。此外,通过使焊区16和17及外部电极24和25进行Ni-Au电镀,形成电镀膜。
接着,如图2所示,包含在坩埚51中的基于硅氧烷的树脂40和层叠基板主体2一起放置在炉50中来密封,并由加热器52加热。此时,作为基于硅氧烷的树脂40的一种成分的硅氧烷42被蒸发以沉积在层叠基板主体2的表面上。如此,包括焊区16和17及外部电极24和25的整个层叠基板主体2用硅氧烷PVD(物理气相沉积)保护膜覆盖。将硅氧烷PVD保护膜(下文中称为硅氧烷膜)的厚度设置成低于100nm。在图1中,未示出硅氧烷膜。
由于硅氧烷膜是通过PVD工艺而不是CVD(化学气相沉积)工艺或等离子体工艺形成的,因为仅需要将硅氧烷膜和基于硅氧烷的树脂40一起加热,所以可容易地且低成本地形成硅氧烷膜。
用于基于硅氧烷的树脂40的固化条件例如是150℃、2小时。当基于硅氧烷的树脂40被固化时,其成分硅氧烷42被蒸发,炉50中的硅氧烷的浓度在150℃下变得最高,并且与蒸发一起,还发生层叠基板主体2的表面上的沉积。在基于硅氧烷的树脂40被固化后,当炉50中的温度降低时,随着其饱和蒸气压变小,硅氧烷42进一步沉积在层叠基板主体2的表面上。
图3是示出放置在炉50中的基于硅氧烷的树脂40的量与形成于层叠基板主体2上的硅氧烷膜的厚度之间的关系的图。如果炉50中的基于硅氧烷的树脂40低于10g/m3,则通过改变基于硅氧烷的树脂40的量,可调节硅氧烷膜的膜厚。如果炉50中的基于硅氧烷的树脂40是10g/m3或更多,则膜厚变为约20nm的恒定值。这是因为炉50中的硅氧烷的浓度饱和了。
对于如此制成的层叠基板主体2评价表1中所示的项。为了比较,同样评价了其上未形成硅氧烷膜的层叠基板主体。在85℃、85%RH和50VDC的测试条件下评价了迁移的发生。通过使基板主体2处于硫化氢的气氛中一分钟来评价硫化。当用Sn-Pb焊料浸渍的2mm×2mm的正方形焊区的95%或更多被焊料浸润时,将焊料的润湿性确定为可接受。当2mm×2mm的正方形焊区接合到引线并具有2gf或更大的接合强度时,将引线可接合性确定为可接受。
表1
硅氧烷PVD保护膜 | 存在 | 不存在 |
迁移的发生 | 没有 | 发生 |
硫化的评价 | 可接受 | 在边缘部分沉淀硫化银 |
焊料润湿性 | 可接受 | 可接受 |
引线接合性 | 最小:3.9gf | 最小:4.0gf |
正如从表1中所清楚的,因为硅氧烷膜覆盖包括焊区16和17以及外部电极24和25的整个层叠基板主体2,所以显著地改进了迁移性质。这是由于硅氧烷膜的防水效应。图4是示出放置在炉50中的基于硅氧烷的树脂40的量和层叠基板主体2的润湿面积之间的关系的图。
此外,也改进了诸如硫化和氧化之类的环境特性。因为硅氧烷膜通过PVD工艺形成,硅氧烷膜形成于微级缺陷内,因此,甚至还可抑制起源于微缺陷的迁移或硫化。
同时,因为硅氧烷膜的厚度很薄,低于100nm,所以焊区16和17及外部电极24和25的焊料润湿性和引线接合性的安装性水平是可接受的。
接着,覆盖层叠基板主体2的硅氧烷膜的表面通过借助诸如等离子体(较佳的是氧等离子体)照射或紫外线照射之类的工艺的清洗来活化。这允许相对于树脂密封材料4的润湿性的进一步改进。此后,安装组件11的外部电极13和14经由焊料19电连接并固定到层叠基板主体2的焊区16和17。
接着,用于密封安装组件11的树脂密封材料4在层叠基板主体2上形成。关于树脂密封材料4的材料,诸如基于环氧的树脂之类的热固化树脂或光敏树脂是理想的。因为树脂密封材料4相对于硅氧烷膜具有良好的润湿性,并且硅氧烷薄膜和层叠基板主体2之间的接合强度也很高,所以可增强树脂密封材料4和层叠基板主体2之间的接合强度。
此外,安装组件11的焊接可在硅氧烷膜的形成之前或之后进行。表2是示出当安装组件11的焊接在硅氧烷膜的形成之前和之后进行时陶瓷多层基板的评价结果的表。
换言之,试样1是其中在将安装组件11焊接到层叠基板主体2后,在层叠基板主体2上形成硅氧烷膜并用树脂密封材料4密封的陶瓷多层基板。试样2是其中在硅氧烷膜覆盖层叠基板主体2后,将安装组件11焊接到层叠基板主体2并用树脂密封材料4密封的陶瓷多层基板。为了比较,试样3是其中在不在层叠基板主体2上形成硅氧烷膜的情况下将安装组件11焊接到层叠基板主体2上并用树脂密封材料4密封的陶瓷多层基板。
表2
热循环测试存在或不存在剥离 | 回流测试 | ||
存在或不存在剥离 | 存在或不存在焊料不足 | ||
试样1 | 0/10 | 0/10 | 0/10 |
试样2 | 0/10 | 0/10 | 0/10 |
试样3 | 1/1 0 | 2/10 | 1/10 |
热循环测试在-55℃/+125℃下进行400次循环,并且树脂密封材料4和层叠基板主体2之间的剥离状态在侧面和横截面处确认。湿气吸收后的焊料回流测试通过使试样处于60℃和60%RH的条件下40小时,随后在260℃下回流试样5次来进行,并且树脂密封材料4和层叠基板主体2之间的剥离状态在侧面和横截面处确认,并确认了焊料不足。
第一实施例的修改(参见图5)
此外,图5中所示的陶瓷多层基板1A基本由层叠基板主体2A、包含在设置在层叠基板主体2A上的空腔65中的安装组件11以及用于密封安装组件11的树脂密封材料4A组成。
在层叠基板主体2A的空腔65中的台阶的上侧上,形成焊区16和17。安装组件11被设置在空腔65中,且其外部电极13和14通过引线接合61电连接到焊区16和17。
在层叠基板主体2A的内部,形成内部导体图案22和23。内部导体图案22的一端和内部导体图案23的一端分别经由形成于层叠基板主体2A中的通孔导体20电连接到焊区16和17。内部导体图案22和23的另一端分别电连接到外部电极24和24。
在焊区16和17上并且在外部电极24和25上,形成Ni-Au电镀膜。此外,用硅氧烷膜覆盖包括焊区16和17及外部电极24和25的整个层叠基板主体2A。将硅氧烷膜的厚度设置成低于100nm。在图5中,未示出硅氧烷膜。
此外,将用于密封安装组件11的树脂密封材料4A填充在层叠基板主体2A的空腔65中。关于树脂密封材料4A的材料,诸如基于环氧的树脂之类的热固化树脂或光敏树脂是理想的。
在由上述构造组成的陶瓷多层基板1A中,因为硅氧烷膜覆盖包括焊区16和17及外部电极24和25的整个层叠基板主体2A,所以显著地改进了迁移性质。同时,因为硅氧烷膜的厚度很薄,低于100nm,所以焊区16和17及外部电极24和25的焊料润湿性和引线接合性的安装性水平是可接受的。引线接合可在硅氧烷膜的形成之前或之后进行。此外,因为树脂密封材料4A相对于硅氧烷膜具有良好的润湿性,并且硅氧烷膜和层叠基板主体2A之间的接合强度也很高,所以可增强树脂密封材料4和层叠基板主体2之间的接合强度。
第二实施例(参见图6)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第二实施例。图6中所示的陶瓷多层基板1B是由层叠基板主体2、形成于层叠基板主体2的上表面上的焊区16以及被设置成覆盖层叠基板主体2和焊区16的硅氧烷膜70组成。在层叠基板主体2的内部,形成用于在形成于层之间的界面处的导体图案22与形成于层之间的另一个界面处另一个导体图案22或焊区16之间进行连接的通孔20。
层叠基板主体2通过以下制造工序来制造。首先,将由SiO2、Al2O3、B2O3和CaO制成的结晶玻璃粉末和氧化铝粉末以相等的重量比混和。通过将15份重量的聚乙烯醇缩丁醛、40份重量的异丙醇和20份重量的trole添加到100份重量的混和粉末中,并且在球磨机中混和24小时,制成一种浆体。通过借助刮浆刀工艺使浆体形成120μm厚的板,获得陶瓷印刷电路基板。
接着,在预定的陶瓷印刷电路基板中形成用于通孔的孔。随后,在用于通孔的孔中填充导电胶以形成通孔导体20,且内部导体图案22通过丝网印刷工艺形成于每一个陶瓷印刷电路基板上。此外,在内部导体图案22通过丝网印刷工艺形成于每一个陶瓷印刷电路基板上的同时,通孔导体20可通过在用于通孔的孔中填充导电胶来形成。
在层叠后,陶瓷印刷电路基板在50MPa的压力下以及60℃温度下接触接合以形成层叠块。在将层叠块切成具有预定尺寸的片后,将这些片一次全部烧结。由此,它们被形成为低温烧结陶瓷层叠基板主体2。
接着,通过在层叠基板主体2的表面上涂导电胶,以及随后对其进行烘焙,形成焊区16。另外,可通过在陶瓷印刷电路基板上形成焊区图案并通过同时烧结焊区图案和陶瓷印刷电路基板来形成焊区16。此外,通过使焊区16进行Ni-Au电镀,形成电镀膜。另外,可以不形成电镀膜。
接着,通过类似于上述第一实施例的方法,通过在层叠基板主体2上形成具有小于100nm厚度的硅氧烷膜70以便覆盖层叠基板主体2和焊区16来制成陶瓷多层基板1B。此外,在图6中,尽管层叠基板主体2的整个表面用硅氧烷膜来覆盖,但至少应覆盖其上形成焊区16的主表面,例如,可以不覆盖底面。
在由上述构造组成的陶瓷多层基板1B中,因为硅氧烷膜70覆盖包括焊区16的整个层叠基板主体2,所以显著地改进了抗迁移性,并且也改进了诸如硫化和氧化之类的环境特性。同时,因为硅氧烷膜70的厚度很薄,低于100nm,所以焊区16的焊料润湿性和引线接合性的安装性水平是可接受的。
第三实施例(参见图7)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第三实施例。图7中所示的陶瓷多层基板1C基本由层叠基板主体2、安装在层叠基板主体2上的安装组件11以及被设置成覆盖层叠基板主体2和安装组件11的硅氧烷膜70组成。
在层叠基板主体2的上表面上,形成焊区16。安装组件11被安装在层叠基板主体2上,设置在安装组件11的底面上的外部电极经由焊料19接合到焊区16。焊区16的未与焊料19接触并曝露的这一部分的至少一部分用硅氧烷膜70覆盖。焊料19的曝露并且未与焊区16和外部电极13接触的部分的至少一部分用硅氧烷膜70覆盖。在层叠基板主体2的内部,形成用于在形成于层之间的界面处的导体图案22与形成于层之间的另一个界面处的另一个导体图案22或焊区16之间进行连接的通孔20。此外,在图7中,对于安装组件11中其外部电极13形成于其底面上的安装组件11,在形成于安装组件11的中心处的外部电极13的侧面上以及在连接到外部电极13的焊料19的侧面上,没有形成硅氧烷膜70,然而在这些部分上可以形成硅氧烷膜70。
陶瓷多层基板1C通过以下制造工序来制造。层叠基板主体2通过类似于上述第二实施例的方法来形成。接着,通过类似于上述第一实施例的方法,形成具有低于100nm的厚度的硅氧烷膜70。接着,经由焊料9将安装组件11安装在其上形成了硅氧烷膜70的焊区16上。此后,通过类似于上述第一实施例的方法,再次形成硅氧烷膜70以覆盖安装组件11和焊料19的未与焊区16和外部电极13接触并曝露的这一部分的至少一部分。此外,此时,硅氧烷膜70可进一步形成于层叠基板主体2上。
在由上述构造组成的陶瓷多层基板1C中,因为硅氧烷膜70覆盖包括焊区16的整个层叠基板主体2,所以显著地改进了抗迁移性,并且也改进了诸如硫化和氧化之类的环境特性。此外,因为安装组件11也用硅氧烷膜70来覆盖,因此也改进了安装组件11的诸如硫化和氧化之类的化学环境特性。同时,因为硅氧烷膜70的厚度很薄,低于100nm,所以焊区16的焊料润湿性和引线接合性的安装性水平是可接受的。此外,因为硅氧烷膜70覆盖焊料19的至少一部分,因此在将陶瓷基板1C安装到其它基板上时的回流步骤中,抑制了焊料19的流出。
第四实施例(参见图8)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第四实施例。图8中所示的陶瓷多层基板1D基本由层叠基板主体2、安装在层叠基板主体2上的安装组件11以及被设置成覆盖层叠基板主体2和安装组件11的硅氧烷膜70组成。
在层叠基板主体2的上表面上,形成焊区16。安装组件11被安装在层叠基板主体2上,设置在安装组件11的底面上的外部电极13经由焊料19连接到焊区16。焊区16的曝露且未与焊料19接触的至少一部分用硅氧烷膜70覆盖。此外,焊料19的未与焊区16和外部电极13接触且曝露的这一部分的至少一部分用硅氧烷膜70覆盖。
在层叠基板主体2的内部,形成用于在形成于层之间的界面处的导体图案22与形成于层之间的另一个界面处的另一个导体图案22或焊区16之间进行连接的通孔20。此外,在图8中,对于安装组件11中其外部电极13形成于其底面上的安装组件,在形成于安装组件11的中心处的外部电极13的侧面上以及在连接到外部电极13的焊料19和焊区16的侧面上,没有形成硅氧烷膜70,然而,在这些部分上可以形成硅氧烷膜70。
陶瓷多层基板1D通过以下制造工序来制造。层叠基板主体2通过类似于上述第二实施例的方法来形成。接着,将安装组件11经由焊料9安装到焊区16上。此后,通过类似于上述第一实施例的方法,再次形成硅氧烷膜70以覆盖安装组件11和焊料19的未与焊区16和外部电极13接触并曝露的这一部分的至少一部分。
在由上述构造组成的陶瓷多层基板1D中,因为硅氧烷膜70覆盖层叠基板主体2和安装组件11以及焊区16的至少一部分,所以显著地改进了抗迁移性,并且也改进了诸如硫化和氧化之类的环境特性。此外,因为安装组件11也用硅氧烷膜70来覆盖,因此也改进了安装组件11的诸如硫化和氧化之类的化学环境特性。此外,因为硅氧烷膜70覆盖焊料19的至少一部分,因此在将陶瓷多层基板1D安装到其它基板上时的回流步骤中,抑制了焊料19的流出。
第五实施例(参见图9)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第五实施例。图9中所示的陶瓷多层基板1E由层叠基板主体1B(参见第二实施例和图6)、安装在层叠基板主体1B上的安装组件11、用于密封安装组件的树脂密封材料4以及被设置成覆盖树脂密封材料4的硅氧烷膜70组成。
在陶瓷多层基板1B的上表面上,形成覆盖有硅氧烷膜70的焊区16。安装组件11被安装在层叠基板主体2上,设置在安装组件11的底面上的外部电极13经由焊料19连接到焊区16。
陶瓷多层基板1E通过以下制造工序来制造。覆盖通过类似于上述第二实施例方法制造的陶瓷多层基板1B的硅氧烷膜70的表面通过借助诸如等离子体(较佳的是氧等离子体)照射或紫外线照射之类的工艺的清洗来活化。接着,在陶瓷多层基板1B的焊区16上,安装组件经由焊料19来安装。接着形成用于密封安装组件11的树脂密封材料4。关于树脂密封材料4的材料,可采用类似于第一实施例中所述的材料。此后,通过类似于上述第一实施例的方法,形成硅氧烷膜70以覆盖树脂密封材料4。此外,此时,可进一步在层叠基板主体2上形成硅氧烷膜70。在图9中,尽管硅氧烷膜70在树脂密封材料4上形成,但相反,可以不形成硅氧烷膜70以覆盖树脂密封材料4。
第五实施例的修改(参见图10和图11)
类似地,关于图10和图11所示的陶瓷多层基板1F和1G,它们各自包括陶瓷多层基板1C(参见第三实施例和图7)和其上形成硅氧烷膜70的树脂密封材料4,以及陶瓷多层基板1D(参见第四实施例和图8)和其上形成硅氧烷膜70的树脂密封材料4。用于形成树脂密封材料4和硅氧烷膜70的方法类似于第一实施例中的方法。尽管在图10和图11中硅氧烷膜70在树脂密封材料4上形成,但相反,可以不形成硅氧烷膜70以覆盖树脂密封材料4。
在由上述构造组成的陶瓷多层基板1E、1F和1G中,除陶瓷多层基板1B、1C和1D的效果外,可获得以下效果。因为硅氧烷膜70在树脂密封材料4和层叠基板主体2之间的界面上形成,所以可增强树脂密封材料4和层叠基板主体2之间的接合强度。当树脂密封材料4用硅氧烷膜70覆盖时,可抑制树脂密封材料4的湿气吸收,从而能够抑制由于树脂密封材料4吸收的湿气引起的安装组件11的特性改变,或由树脂密封材料4的水解分裂导致的杂质。此外,当硅氧烷膜70覆盖树脂密封材料4和层叠基板主体2之间的界面的侧面时,可更加确定地抑制层叠基板主体2和树脂密封材料4之间的界面的剥离。
第六实施例(参见图12)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第六实施例。图12中所示的陶瓷多层基板1H是由层叠基板主体2、安装在层叠基板主体2上的安装组件11、用于密封安装组件11的树脂密封材料4以及被设置成覆盖层叠基板主体2和树脂密封材料4的硅氧烷膜70组成。
在层叠基板主体2的上表面上,形成焊区16。安装组件11被安装在层叠基板主体2上,设置在安装组件11的底面上的外部电极13经由焊料19连接到焊区16。
陶瓷多层基板1H通过以下制造工序来制造。在通过类似于第二实施例的方法制成的陶瓷多层基板2的焊区16上,安装组件11经由焊料19安装。接着,形成用于密封安装组件11的树脂密封材料4。关于树脂密封材料4的材料,可采用类似于第一实施例中所述的材料。此后,通过类似于第一实施例的方法,形成硅氧烷膜以覆盖层叠基板主体2和树脂密封材料4。
在由上述构造组成的陶瓷多层基板1H中,因为树脂密封材料4用硅氧烷膜70覆盖,所以可抑制树脂密封材料4的湿气吸收,从而能够抑制由于树脂密封材料4吸收的湿气引起的安装组件11的特性改变,或由树脂密封材料4的水解分裂导致的杂质。此外,当硅氧烷膜70覆盖树脂密封材料4和层叠基板主体2之间的界面的侧面时,可更加确定地抑制层叠基板主体2和树脂密封材料4之间的界面的剥离。
第七实施例(参见图13)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第七实施例。图13(a)中所示的陶瓷多层基板1I是由层叠基板主体2、形成于层叠基板主体2的上侧上的焊区16、经由焊料19安装在焊区16上的安装组件11以及被设置成覆盖层叠基板主体2、安装组件11和焊料19的至少一部分的硅氧烷膜70组成。在层叠基板主体2的内部,形成用于在形成于层之间的界面处的导体图案22与形成于层之间的另一个界面处的另一个导体图案22或焊区16之间进行连接的通孔20。
陶瓷多层基板1I通过以下工序来制造。如图13(b)所示,首先,通过类似于上述第二实施例的方法,制造陶瓷多层基板1B,其中层叠基板主体2和形成于层叠基板主体2的上表面上的焊区16用硅氧烷膜70覆盖。同时,焊球19A在安装组件11的外部电极13上形成,此后,形成硅氧烷膜70以覆盖安装组件11和焊球19A。硅氧烷膜70通过类似于上述第一实施例的方法来形成。接着,通过将覆盖有硅氧烷膜70的安装组件11排列在陶瓷多层基板1B上以使焊球19A和焊区16各自对应,并使安装组件11受到热处理,将安装组件11连接到陶瓷多层基板1B的上表面,从而导致陶瓷多层基板1I的制造。
在由上述构造组成的陶瓷多层基板1I中,因为硅氧烷膜70覆盖焊区16的未与焊料19接触的侧面和整个层叠基板主体2,所以显著地改进了抗迁移性,从而也改进了诸如硫化和氧化之类的环境特性。此外,因为安装组件11也用硅氧烷膜70来覆盖,因此也改进了安装组件11的诸如硫化和氧化之类的化学环境特性。此外,因为未与焊区16和安装组件11的外部电极13接触的焊料19的所有侧面都用硅氧烷膜70覆盖,所以在将陶瓷多层基板1I安装到其它基板上时的回流步骤中,确定地抑制了焊料19的流出。同时,因为硅氧烷膜70的厚度很薄,低于100nm,所以由于焊接步骤中的热处理导致硅氧烷膜被去除,从而经由焊料的连接性是可接受的。
第八实施例(参见图14)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第八实施例。图14(a)中所示的陶瓷多层基板1J由层叠基板主体2、形成于层叠基板主体2的上侧上的焊区16、经由焊料19安装在焊区16上的安装组件11以及被设置成覆盖层叠基板主体2、安装组件11和焊料19的至少一部分的硅氧烷膜70组成。在层叠基板主体2的内部,形成用于在形成于层之间的界面处的导体图案22与形成于层之间的另一个界面处的另一个导体图案22或焊区16之间进行连接的通孔20。
陶瓷多层基板1J通过以下工序来制造。如图14(b)所示,首先,在形成于层叠基板主体2的上表面上的焊区16上形成焊球19A。接着,形成硅氧烷膜70以覆盖层叠基板主体2和焊球19A。同时,形成硅氧烷膜70以覆盖安装组件70及其外部电极13。硅氧烷膜70通过类似于第一实施例的方法来形成。接着,通过将覆盖有硅氧烷膜70的安装组件11排列在陶瓷多层基板1B上以使焊球19A和焊区16各自对应,并使安装组件11受到热处理,将安装组件11连接到层叠基板主体2的上表面,从而导致陶瓷多层基板1J的制造。
在由上述构造组成的陶瓷多层基板1J中,因为硅氧烷膜70覆盖焊区16的未与焊料19接触的侧面和整个层叠基板主体2,所以显著地改进了抗迁移性,从而也改进了诸如硫化和氧化之类的环境特性。此外,因为安装组件11也用硅氧烷膜70来覆盖,因此也改进了安装组件11的诸如硫化和氧化之类的化学环境特性。此外,因为未与焊区16和安装组件11的外部电极13接触的焊料19的所有侧面都用硅氧烷膜70覆盖,所以在将陶瓷多层基板1J安装到其它基板上时的回流步骤中,确定地抑制了焊料19的流出。同时,因为硅氧烷膜70的厚度很薄,低于100nm,所以由于焊接步骤中的热处理导致硅氧烷膜被去除,从而经由焊料的连接性是可接受的。
第九实施例(参见图15)
接着,将描述根据本发明的陶瓷多层基板及其制造方法的第九实施例。图15中所示的陶瓷多层基板1K由层叠基板主体1I(参见第七实施例和图13)或层叠基板主体1J(参见第八实施例和图14)、用于密封陶瓷多层基板1I或1J上的安装组件11的树脂密封材料4以及被设置成覆盖树脂密封材料4的硅氧烷膜70组成。
陶瓷多层基板1K通过以下工序来制造。覆盖通过类似于上述第七和第八实施例方法制造的陶瓷多层基板1I或1J的硅氧烷膜70的表面通过借助诸如等离子体(较佳的是氧等离子体)照射或紫外线照射之类的工艺的清洗来活化。接着,在陶瓷多层基板1I或1J上,形成用于密封安装组件11的树脂密封材料4。关于树脂密封材料4的材料,可采用类似于第一实施例中所述的材料。此后,通过类似于上述第一实施例的方法,形成硅氧烷膜70以覆盖树脂密封材料4。此外,此时,可进一步在层叠基板主体2上形成硅氧烷膜70。在图15中,尽管硅氧烷膜70在树脂密封材料4上形成,但相反,可以不形成硅氧烷膜70以覆盖树脂密封材料4。
在由上述构造组成的陶瓷多层基板1K中,除陶瓷多层基板1I和1J的效果外,可获得以下效果。因为硅氧烷膜70在树脂密封材料4和层叠基板主体2之间的界面上形成,所以可增强树脂密封材料4和层叠基板主体2之间的接合强度。当树脂密封材料4用硅氧烷膜70覆盖时,可抑制树脂密封材料4的湿气吸收,从而能够抑制由于树脂密封材料4吸收的湿气引起的安装组件11的特性改变,或由树脂密封材料4的水解分裂导致的杂质。此外,当硅氧烷膜70覆盖树脂密封材料4和层叠基板主体2之间的界面的侧面时,可更加确定地抑制层叠基板主体2和树脂密封材料4之间的界面的剥离。
另一个实施例
此外,根据本发明的陶瓷多层基板及其制造方法不旨在限于上述实施例,相反,它们可在本发明的范围内以不同的方式改变。
例如,在上述实施例中,示出了其中层叠基板主体通过层叠陶瓷印刷电路基板来形成的实施例,然而,其中层叠基板主体通过交替地重涂陶瓷胶和导电胶的方法形成的实施例是可能的。
工业实用性
如上所述,本发明可用于在其表面上安装诸如IC组件之类的电子组件的陶瓷多层基板及其制造方法,特别地,其优点在于抗迁移性良好,且树脂密封材料和陶瓷多层基板之间的接合强度变得较高。
Claims (21)
1.一种陶瓷多层基板,包括:
通过层叠多个陶瓷层和内部导体层组成的层叠基板主体;
设置在所述层叠基板主体的表面上的焊区,用于电连接至安装组件的外部电极;以及
被设置成覆盖所述层叠基板主体和所述焊区的硅氧烷膜,所述硅氧烷膜的厚度低于100nm。
2.如权利要求1所述的陶瓷多层基板,其特征在于,还设置所述硅氧烷膜以覆盖经由焊料安装在所述焊区上的安装组件以及所述焊料的至少一部分。
3.一种陶瓷多层基板,包括:
通过层叠多个陶瓷层和内部导体层组成的层叠基板主体;
设置在所述层叠基板主体的表面上的焊区,用于电连接至安装组件的外部电极;
经由焊料安装到所述焊区上的安装组件;以及
被设置成覆盖所述层叠基板主体、所述安装组件和所述焊料的至少一部分的硅氧烷膜,所述硅氧烷膜的厚度低于100nm。
4.如权利要求1至3中的任一项所述的陶瓷多层基板,其特征在于,还包括用于密封所述安装组件的树脂密封材料。
5.如权利要求4所述的陶瓷多层基板,其特征在于,所述树脂密封材料用所述硅氧烷膜覆盖。
6.一种陶瓷多层基板,包括:
通过层叠多个陶瓷层和内部导体层组成的层叠基板主体;
设置在所述层叠基板主体的表面上的焊区,用于电连接至安装组件的外部电极;
经由焊料安装到所述焊区上的安装组件;
用于密封所述安装组件的树脂密封材料;以及
被设置成覆盖所述层叠基板主体和所述树脂密封材料的硅氧烷膜,所述硅氧烷膜的厚度低于100nm。
7.如权利要求1至6中的任一项所述的陶瓷多层基板,其特征在于,所述安装组件包括IC组件并通过引线接合电连接到所述焊区。
8.如权利要求7所述的陶瓷多层基板,其特征在于,所述IC组件被包含在设置在所述层叠基板主体的主表面上的空腔中。
9.如权利要求1至8中的任一项所述的陶瓷多层基板,其特征在于,在所述焊区上形成电镀膜。
10.一种陶瓷多层基板的制造方法,包括以下步骤:
通过层叠多个陶瓷层和内部导体层形成层叠基板主体;
在所述层叠基板主体的表面上形成焊区,用于电连接至安装组件的外部电极;以及
通过PVD工艺形成厚度低于100nm的硅氧烷膜,以覆盖所述层叠基板主体和所述焊区。
11.如权利要求10所述的陶瓷多层基板的制造方法,其特征在于,还包括以下步骤:
经由焊料在其上形成所述硅氧烷膜的所述焊区上安装所述安装组件;以及
通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖所述安装组件和所述焊料的至少一部分。
12.一种陶瓷多层基板的制造方法,包括以下步骤:
通过层叠多个陶瓷层和内部导体层形成层叠基板主体;
在所述层叠基板主体的表面上形成焊区,用于电连接至安装组件的外部电极;
经由焊料将所述安装组件安装到所述焊区上;以及
通过PVD工艺形成厚度低于100nm的硅氧烷膜,以覆盖所述层叠基板主体、所述安装组件和所述焊料的至少一部分。
13.如权利要求10至12中的任一项所述的陶瓷多层基板的制造方法,其特征在于,还包括在通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖所述安装组件的步骤之后,用密封材料密封所述安装组件的步骤。
14.如权利要求13所述的陶瓷多层基板的制造方法,其特征在于,还包括通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖所述树脂密封材料的步骤。
15.一种陶瓷多层基板的制造方法,包括以下步骤:
通过层叠多个陶瓷层和内部导体层形成层叠基板主体;
在所述层叠基板主体的表面上形成焊区,用于电连接至安装组件的外部电极;
经由焊料将所述安装组件安装到所述焊区上;
用密封材料密封所述安装组件;以及
通过PVD工艺形成厚度低于100nm的硅氧烷膜,以覆盖所述层叠基板主体和所述树脂密封材料。
16.一种陶瓷多层基板的制造方法,包括以下步骤:
通过层叠多个陶瓷层和内部导体层形成层叠基板主体;
在所述层叠基板主体的表面上形成焊区,用于电连接至安装组件的外部电极;
在所述焊区上形成焊球;
通过PVD工艺形成厚度低于100nm的硅氧烷膜,以覆盖所述层叠基板主体、所述焊区和所述焊球;
通过PVD工艺形成厚度低于100nm的另一硅氧烷膜,以覆盖所述安装组件;以及
经由所述焊球将所述安装组件安装到所述焊区上。
17.一种陶瓷多层基板的制造方法,包括以下步骤:
通过层叠多个陶瓷层和内部导体层形成层叠基板主体;
在所述层叠基板主体的表面上形成焊区,用于电连接至安装组件的外部电极;
通过PVD工艺形成厚度低于100nm的硅氧烷膜,以覆盖所述层叠基板主体和所述焊区;
在所述安装组件上形成焊球;
通过PVD工艺形成厚度低于100nm的另一硅氧烷膜,以覆盖所述安装组件和所述焊球;以及
经由所述焊球将所述安装组件安装到所述焊区上。
18.如权利要求16或17所述的陶瓷多层基板的制造方法,其特征在于,还包括在安装所述安装组件的步骤后用树脂密封材料密封所述安装组件的步骤。
19.如权利要求18所述的陶瓷多层基板的制造方法,其特征在于,还包括通过PVD工艺形成厚度低于100nm的硅氧烷膜以覆盖所述层叠基板主体和所述树脂密封材料的步骤。
20.如权利要求10至19中的任一项所述的陶瓷多层基板的制造方法,其特征在于,还包括活化所述硅氧烷膜的表面的步骤。
21.如权利要求20所述的陶瓷多层基板的制造方法,其特征在于,所述活化所述硅氧烷膜的表面的步骤通过使所述硅氧烷膜的表面受到利用氧等离子体的清洗来进行。
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EP (1) | EP1855516A4 (zh) |
JP (1) | JPWO2006093293A1 (zh) |
KR (1) | KR100857011B1 (zh) |
CN (1) | CN101116382A (zh) |
WO (1) | WO2006093293A1 (zh) |
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EP2709150A1 (en) * | 2012-09-18 | 2014-03-19 | ABB Technology AG | Humidity protection of semiconductor modules |
WO2014097835A1 (ja) * | 2012-12-18 | 2014-06-26 | 株式会社村田製作所 | 樹脂多層基板 |
EP2960936A4 (en) * | 2013-02-22 | 2016-10-19 | Hitachi Ltd | RESIN SEALED ELECTRONIC CONTROL DEVICE |
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USRE33691E (en) * | 1984-12-21 | 1991-09-17 | General Electric Company | Piezoelectric ceramic switching devices and systems and method of making the same |
JPS63311794A (ja) * | 1987-06-12 | 1988-12-20 | Sumitomo Electric Ind Ltd | フレキシブル配線板の製造方法 |
DE69116422D1 (de) * | 1990-05-18 | 1996-02-29 | Ibm | Supraleitendes Mehrschichtkeramiksubstrat |
JPH06152111A (ja) * | 1992-11-02 | 1994-05-31 | Matsushita Electric Ind Co Ltd | プリント基板およびその製造方法 |
JPH06152109A (ja) * | 1992-11-02 | 1994-05-31 | Matsushita Electric Ind Co Ltd | プリント基板およびその製造方法 |
US5492730A (en) * | 1992-12-28 | 1996-02-20 | Aluminum Company Of America | Siloxane coating process for metal or ceramic substrates |
JPH06244316A (ja) * | 1993-02-19 | 1994-09-02 | Sony Corp | 半導体装置、その製造方法及びその製造装置 |
JPH0752395A (ja) * | 1993-08-20 | 1995-02-28 | Seiko Epson Corp | インクジェット記録ヘッドの製造方法 |
JP2738303B2 (ja) * | 1994-07-15 | 1998-04-08 | 株式会社デンソー | 電子部品搭載回路基板の製造方法 |
US5600181A (en) * | 1995-05-24 | 1997-02-04 | Lockheed Martin Corporation | Hermetically sealed high density multi-chip package |
WO1997010282A1 (en) * | 1995-09-12 | 1997-03-20 | Gelest, Inc. | Beta-substituted organosilsesquioxanes and use thereof |
US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
JPH10293201A (ja) * | 1997-04-17 | 1998-11-04 | Ito Kogaku Kogyo Kk | 撥水処理光学要素 |
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JP3883094B2 (ja) * | 1999-05-28 | 2007-02-21 | 富士通株式会社 | ヘッドicチップの製造方法 |
DE19930782A1 (de) * | 1999-07-03 | 2001-01-04 | Bosch Gmbh Robert | Verfahren zum selektiven Beschichten keramischer Oberflächenbereiche |
JP2001085823A (ja) * | 1999-09-17 | 2001-03-30 | Denso Corp | 電子部品の実装構造 |
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JP3663120B2 (ja) * | 2000-09-04 | 2005-06-22 | 株式会社日立製作所 | 自動車用エンジンコントロールユニットの実装構造及び実装方法 |
DE10114897A1 (de) * | 2001-03-26 | 2002-10-24 | Infineon Technologies Ag | Elektronisches Bauteil |
JP2003249840A (ja) * | 2001-12-18 | 2003-09-05 | Murata Mfg Co Ltd | 弾性表面波装置 |
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JP2004247334A (ja) * | 2003-02-10 | 2004-09-02 | Murata Mfg Co Ltd | 積層型セラミック電子部品およびその製造方法ならびにセラミックグリーンシート積層構造物 |
JP2005108950A (ja) * | 2003-09-29 | 2005-04-21 | Matsushita Electric Ind Co Ltd | セラミックモジュール部品およびその製造方法 |
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2006
- 2006-03-03 EP EP06715221A patent/EP1855516A4/en not_active Withdrawn
- 2006-03-03 KR KR1020077016249A patent/KR100857011B1/ko active IP Right Grant
- 2006-03-03 CN CNA2006800040962A patent/CN101116382A/zh active Pending
- 2006-03-03 WO PCT/JP2006/304162 patent/WO2006093293A1/ja active Application Filing
- 2006-03-03 JP JP2006524158A patent/JPWO2006093293A1/ja active Pending
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2007
- 2007-07-13 US US11/777,354 patent/US20070256859A1/en not_active Abandoned
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EP1855516A1 (en) | 2007-11-14 |
US20090321121A1 (en) | 2009-12-31 |
KR20070094787A (ko) | 2007-09-21 |
WO2006093293A1 (ja) | 2006-09-08 |
US20070256859A1 (en) | 2007-11-08 |
KR100857011B1 (ko) | 2008-09-04 |
JPWO2006093293A1 (ja) | 2008-08-07 |
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