CN101083266A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN101083266A
CN101083266A CNA2007101266426A CN200710126642A CN101083266A CN 101083266 A CN101083266 A CN 101083266A CN A2007101266426 A CNA2007101266426 A CN A2007101266426A CN 200710126642 A CN200710126642 A CN 200710126642A CN 101083266 A CN101083266 A CN 101083266A
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mos transistor
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高桥秀一
山田裕
金井胜
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Sanyo Electric Co Ltd
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
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    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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Abstract

本发明的目的是提供可靠性高的电阻。此外，本发明的目的是实现在同一半导体基板上混载有MOS晶体管和电阻的半导体装置的小型化。在P型半导体基板(10)的表面上形成N型阱区域(11)，在该阱区域11的表面上形成P－型电阻层(20)。并且，在阱区域(11)上环状地围绕电阻层(20)形成导电层(30)。在通常动作中，向导电层(30)施加规定的电压，没有在导电层(30)的下部形成沟道，从而将其他元件(例如P沟道型MOS晶体管1)与下拉电阻(2)分离。电阻层(20)与元件分离绝缘膜不接触。在由元件分离绝缘膜围绕的一个区域内形成PMOS(1)和下拉电阻(2)这两者。

Description

半导体装置
技术领域
本发明涉及半导体装置，尤其涉及在同一半导体基板上包括MOS晶体管和电阻的半导体装置。
背景技术
目前，在同一半导体基板上混载有MOS晶体管和电阻的半导体装置的是公知的。作为利用这样的半导体装置的电路，已知地有荧光显示管的驱动电路。荧光显示管也被称为VFD(Vacuum Fluorescent Display)，是在真空容器内从阴极飞出的电子由栅电极(grid electrode)控制并且与阳极上的荧光体干涉而发光的元件。荧光显示管用作音频装置、时钟、电子计算机等的数字显示部。
为了使这样的荧光显示管发光，阳极和栅电极上必需高压，并且驱动电路的输出级一般如下构成。如图2所示，该驱动电路的输出级包括在输出端子Out和电源电压VDD之间连接的P沟道型MOS晶体管(以下称为PMOS)100、在PMOS 100的漏极侧和负电压供给端子101之间连接的下拉(pull down)电阻102。此外，PMOS 100的后栅极与电源电压VDD连接。输出端子Out与未图示的栅电极和阳极连接。
对PMOS 100的栅极施加未图示的理论电路的输出信号(驱动信号DRV)，由此来控制PMOS 100的导通/截止。并且通过PMOS 100的控制，向栅电极和阳极提供规定的电压(高电平和低电平)。电源电压VDD例如是约5V，负电压供给端子101提供-30～-40V左右的负电压。
接下来，参考图3说明PMOS 100的设备结构。图3(a)是POMS 100的平面图，图3(b)是沿图3(a)的Y-Y线的截面图。该PMOS 100构成为将多个MOS晶体管结构作为整体而形成一个耐高压的PMOS 100。
如图3(a)、(b)所示，在PMOS 100的形成区域中，在P型半导体基板105的表面上形成N型阱区域106，在该阱区域106上通过硅的局部氧化(ロコス，LOCOS(Local Oxidation of Silicon))法等形成元件分离绝缘膜107。此外，在没有形成元件分离绝缘膜107的半导体基板105(阱区域106)的表面上分别通过栅极绝缘膜(未示出)形成多个环状栅极108。此外，在由栅极108包围的半导体基板105(阱区域106)的表面上形成P-型低浓度漏区域109，在低浓度漏区域109的表面上形成接触用的P+型高浓度漏区域110。此外，在栅极108的环外的半导体基板105(阱区域106)的表面上围绕各栅极108的周围形成与低浓度漏区域109相对应的P+型高浓度源区域111。
在包括栅极108的半导体基板105的表面上形成有层间绝缘膜112，在该层间绝缘膜112上形成有连接到高浓度漏区域110和高浓度源区域111的接触(contact)部113。此外，在该接触部113上形成有布线层114、115。布线层114是与各高浓度源区域111公共连接的布线层，布线层115是与各高浓度源区域110共同连接的布线层。布线层114与电源电压VDD连接，布线层115与输出端子Out及后述下拉电阻102的一端连接。此外，对各栅极108施加驱动信号DRV。
接下来，参考图4说明下拉电阻102的设备结构。图4(a)是下拉电阻102的平面图，图4(b)是沿图4(a)中的Z-Z线的截面图。
如图4(a)、(b)所示，在下拉电阻102的形成区域中，在半导体基板105的表面上形成N型阱区域120，在该阱区域120内通过硅的局部氧化法等形成用于对该下拉电阻102和其他元件(上述PMOS100等)进行元件分离的元件分子绝缘膜121。在由元件分离绝缘膜121包围的阱区域120表面上形成注入了低浓度P型杂质的P-型电阻层122，进一步地岛状地形成注入了高浓度P型杂质的P+型电极取出层123。
在对置的电极取出层123间注入用于抑制电压依赖性的P型杂质离子，形成杂质层124(FP)。在电极取出层123上形成接触部125、126，在该接触部125、126上形成布线层127、128。一侧接触部125通过布线层127与上述PMOS 105的漏极侧和输出端子Out连接，另一侧接触部126通过布线层128与负电压供给端子101连接。
上述技术在例如下列专利文献中记载。
但是，上述电阻(下拉电阻102)与电阻层122邻接并且形成元件分离绝缘膜121。因此，在元件分离绝缘膜121的端部聚集应力，可能造成电阻层122和阱区域120之间的耐压强度(耐压)恶化。
此外，由于近年来半导体集成电路的高密度化、多功能化，因此要求各种半导体元件的面积可以限定地更小。因此，优选，混载上述这种MOS晶体管和电阻的半导体装置也可以限定地更小。
【专利文献1】特开平9-26758号公报
【专利文献2】特开2003-224267号公报
发明内容
在此，本发明的目的是提供可靠性高的电阻。此外，本发明的目的是实现在同一半导体基板上混载MOS晶体管和电阻的半导体装置的小型化。
本发明是鉴于上述问题而提出来的，其主要特征如下所述。即，本发明的半导体装置在第一导电型半导体基板上具备MOS晶体管和电阻，所述MOS晶体管形成在所述半导体基板表面上形成的第二导电型阱层内，在所述阱层上形成元件分离绝缘膜，所述电阻包括：第一导电型电阻层，其形成在与所述MOS晶体管形成的阱层相同的阱层内，并且形成在所述阱层的表面上；以及导电层，其在所述阱层上，围绕所述电阻层并形成为环状，由所述元件分离绝缘膜包围的一个区域内形成有所述MOS晶体管和所述电阻这两者。
本发明构成为由导电层包围电阻层而不与元件分离绝缘膜接触。因此，可以避免因在元件分离绝缘膜的端部聚集应力而使耐压强度恶化，并且可以提高电阻的可靠性。此外，在由元件分离绝缘膜包围的一个区域内形成MOS晶体管和电阻这两者的情况下，不需要存在于现有MOS晶体管和电阻之间的元件分离绝缘膜的长间隙，从而可以实现半导体装置的小型化。
附图说明
图1是说明本发明实施方式相关的半导体装置的平面图和截面图。
图2是说明本发明以及现有实施方式相关的半导体装置的电路图。
图3是说明现有的半导体装置的平面图和截面图。
图4是说明现有的半导体装置的平面图和截面图。
1-P沟道型MOS晶体管；2-下拉电阻；10-半导体基板；11-阱区域；12-栅极；13-低浓度漏区域；14-高浓度漏区域；15-高浓度源区域；16-接触部；17-布线层；18-布线层；20-电阻层；21-电极取出层；22-杂质层；23-接触部；24-接触部；25-布线层；26-布线层；30-导电层；31-层间绝缘膜；32-元件分离绝缘膜；100-P沟道型MOS晶体管；101-负电压供给端子；102-下拉电阻；105-半导体基板；106-阱区域；107-元件分离绝缘膜；108-栅极；109-低浓度漏区域；110-高浓度漏区域；111-高浓度源区域；112-层间绝缘膜；113-接触部；114-布线层；115-布线层；120-阱区域；121-元件分离绝缘膜；122-电阻层；123-电极取出层；124-杂质层；125-接触部；126-接触部；127-布线层；128-布线层；VDD-电源电压；DRV-驱动信号；Out-输出端子。
具体实施方式
接下来，参考图1和图2说明根据用于实施本发明的最佳方式的半导体装置。由于采用本实施方式的半导体装置的荧光显示管的驱动电路的电路图结构与现有技术(图2)相同，所以为了简略而省略其说明，主要详细地说明设备结构。图1(a)是本实施方式相关的半导体装置的平面图，图1(b)是沿图1(a)中的X-X线的截面图。
该半导体装置从较大的方面分为由PMOS 1区域和下拉电阻2的区域构成。PMOS1构成为将多个P沟道型MOS晶体管结构作为整体形成一个耐高压的PMOS1。此外，当然也可以由一个P沟道型MOS晶体管结构和电阻构成。另外，也可以配置多个与下拉电阻2相同的电阻。
首先，说明PMOS1。如图1(a)、(b)所示，在P型半导体基板10的表面上形成N型阱区域11。
此外，在半导体基板10(阱区域11)的表面上分别通过栅极绝缘膜(未图示)环状地形成栅极12。此外，在由栅极12围绕的半导体基板10(阱区域11)的表面上形成P-型低浓度漏区域13，在低浓度漏区域13的表面上形成接触用的P+型高浓度漏区域14。在栅极12环外的半导体基板10(阱区域11)的表面上，围绕各栅极12形成与低浓度漏区域13相对应的P+型高浓度源区域15。此外，如图1(b)所示，相邻的低浓度漏区域13分别仅间隔规定的间隙L，来补偿耐高压强度。
在高浓度漏区域14和高浓度源区域15上形成接触部16，在该接触部16上形成布线层17、18。布线层17是与各高浓度源区域15公共连接的布线层，布线层18是与各高浓度漏区域14公共连接的布线层。
此外，布线层17与电源电压VDD连接，布线层18与输出端子Out和下述下拉电阻2的一端连接。
接下来，说明下拉电阻2。下拉电阻2形成在阱区域11中除了PMOS1形成区域以外的区域的表面上。在阱区域11的表面上形成用于耐高压的P-型(低浓度)电阻层20，进一步在电阻层20的表面上形成岛状地用于接触的P+型(高浓度)电极取出层21。电阻层20可以通过形成PMOS1的低浓度漏区域13时离子注入的同一工序形成。此外，在本实施方式中，如图1(b)所示，通过将电阻层20、邻近的低浓度漏区域13仅间隔规定距离M来补偿下拉电阻2的耐高压强度。在对置的电极取出层21之间注入用于抑制电压依赖性的P型杂质离子，形成杂质层22(FP)。
在电极取出层21上形成接触部23、24，在该接触部23、24上形成布线层25、26。一侧的接触部23通过布线层25与上述PMOS 1的布线层18连接，进一步地其连接点与输出端子Out连接。另一侧的接触部24通过布线层26与负电压供给端子101连接。
此外，在阱区域11的表面上围绕电阻层20形成导电层30(例如多晶硅层)。该导电层30与电源电压VDD连接。导电层30因MOS晶体管构造而具有所谓的栅极功能，在本实施方式的动作期间将PMOS1和下拉电阻2分离。也就是，在通常动作中为了对导电层30施加规定的高电平(在本实施方式中为电源电压VDD)，没有在导电层30的下部形成沟道，在该导电层30的下部没有剩余的电流流动。此外，在图1(a)中，导电层30通过布线层17与电源电压VDD连接，但是也可以由其他布线与电源电压VDD连接。
导电层30可以通过与PMOS 1的栅极12相同的工序形成，所以制造工序不会变得复杂。
在包含栅极12和导电层30的半导体基板10的表面上形成层间绝缘膜31，在该层间绝缘膜31上形成连接到(至る)高浓度漏区域14、高浓度源区域15和电极取出层21的各接触部16、23、24。此外，围绕所有的PMOS 1和下拉电阻2，通过硅的局部氧化法等形成元件分离绝缘膜32。
这样，根据本实施方式的半导电体装置，在由元件分离绝缘膜(32)围绕的一个区域内可以混载MOS晶体管和电阻这两者。因此，可以减小元件的面积。此外，通过使电阻层(20)和邻接MOS晶体管的杂质区域(在本实施方式中是低浓度漏区域13)的间隙M与MOS晶体管的低浓度杂质区域间的间隙L相同，进一步地使导电层(30)的图案与MOS晶体管的栅极(12)相同，可以补偿MOS晶体管和电阻的耐压强度(耐压)，同时形成最小尺寸的元件。
此外，可以不使用由硅的局部氧化法等形成的元件分离绝缘膜而使用导电层将其他元件与电阻分离。根据上述结构，因为电阻的电阻层不与元件分离绝缘膜接触，所以可以防止耐压强度恶化，提高可靠性。
此外，不言而喻本发明不限定于上述的实施方式，并且在不脱离其主旨的范围下可以改变设计。例如，在上述中下拉电阻也可以构成为上拉电阻。本发明可以广泛地适用于在半导体基板上包括电阻的半导体装置，特别适用于混载有MOS晶体管和电阻这两者的半导体装置。

Claims (3)

1、一种半导体装置，在第一导电型半导体基板上具备MOS晶体管和电阻，其中，
所述MOS晶体管形成在所述半导体基板表面上形成的第二导电型阱层内，
在所述阱层上形成元件分离绝缘膜，
所述电阻包括：
第一导电型电阻层，其形成在与所述MOS晶体管形成的阱层相同的阱层内，并且形成在所述阱层的表面上；以及
导电层，其在所述阱层上，且包围所述电阻层并形成为环状，
在由所述元件分离绝缘膜包围的一个区域内形成有所述MOS晶体管和所述电阻这两者。
2、根据权利要求1所述的半导体装置，其特征在于，
所述MOS晶体管的栅极形成为环状。
3、一种半导体装置，将权利要求1或2中任一项的半导体装置用作荧光显示管驱动电路的一部分，其中，
向所述MOS晶体管的源极和所述导电层施加电源电压，所述电阻的端子与负电压供给端子连接，并且从所述电阻的其他端子和所述MOS晶体管的漏极之间的连接点取出输出。
CNA2007101266426A 2006-06-01 2007-05-29 半导体装置 Pending CN101083266A (zh)

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