CN101071629A - 半导体存储器件 - Google Patents
半导体存储器件 Download PDFInfo
- Publication number
- CN101071629A CN101071629A CNA2007101029134A CN200710102913A CN101071629A CN 101071629 A CN101071629 A CN 101071629A CN A2007101029134 A CNA2007101029134 A CN A2007101029134A CN 200710102913 A CN200710102913 A CN 200710102913A CN 101071629 A CN101071629 A CN 101071629A
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- China
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 68
- 239000012535 impurity Substances 0.000 claims description 61
- 238000009792 diffusion process Methods 0.000 claims description 57
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
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- 238000010168 coupling process Methods 0.000 description 11
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- 238000002955 isolation Methods 0.000 description 10
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- AYNSTGCNKVUQIL-UHFFFAOYSA-N C(CCCCCCCCCCC)C=1C=CC(=C(C=1)C1=NC(=CC(=C1)N(CCN(C)C)C)C1=C(C=CC(=C1)CCCCCCCCCCCC)OC)OC Chemical compound C(CCCCCCCCCCC)C=1C=CC(=C(C=1)C1=NC(=CC(=C1)N(CCN(C)C)C)C1=C(C=CC(=C1)CCCCCCCCCCCC)OC)OC AYNSTGCNKVUQIL-UHFFFAOYSA-N 0.000 description 4
- 101100309034 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RTF1 gene Proteins 0.000 description 4
- 101100166255 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CEP3 gene Proteins 0.000 description 3
- 101100495436 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CSE4 gene Proteins 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
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- 238000004891 communication Methods 0.000 description 1
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006132895A JP5068035B2 (ja) | 2006-05-11 | 2006-05-11 | 半導体記憶装置 |
| JP2006132895 | 2006-05-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101071629A true CN101071629A (zh) | 2007-11-14 |
Family
ID=38684950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101029134A Pending CN101071629A (zh) | 2006-05-11 | 2007-05-11 | 半导体存储器件 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7652927B2 (enExample) |
| JP (1) | JP5068035B2 (enExample) |
| CN (1) | CN101071629A (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169712A (zh) * | 2010-02-26 | 2011-08-31 | 海力士半导体有限公司 | 半导体存储器件 |
| CN104733037A (zh) * | 2015-03-27 | 2015-06-24 | 西安华芯半导体有限公司 | 一种控制字线泄放电流的装置 |
| CN109903790A (zh) * | 2017-12-11 | 2019-06-18 | 旺宏电子股份有限公司 | 存储器装置及其操作方法 |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7606066B2 (en) | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
| US7492632B2 (en) | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
| WO2007128738A1 (en) | 2006-05-02 | 2007-11-15 | Innovative Silicon Sa | Semiconductor memory cell and array using punch-through to program and read same |
| US8069377B2 (en) | 2006-06-26 | 2011-11-29 | Micron Technology, Inc. | Integrated circuit having memory array including ECC and column redundancy and method of operating the same |
| US9601493B2 (en) | 2006-11-29 | 2017-03-21 | Zeno Semiconductor, Inc | Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making |
| US9391079B2 (en) | 2007-11-29 | 2016-07-12 | Zeno Semiconductor, Inc. | Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making |
| US8514622B2 (en) | 2007-11-29 | 2013-08-20 | Zeno Semiconductor, Inc. | Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making |
| US8547756B2 (en) | 2010-10-04 | 2013-10-01 | Zeno Semiconductor, Inc. | Semiconductor memory device having an electrically floating body transistor |
| JP5078338B2 (ja) * | 2006-12-12 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| KR101277402B1 (ko) | 2007-01-26 | 2013-06-20 | 마이크론 테크놀로지, 인코포레이티드 | 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 dram 트랜지스터 |
| US8518774B2 (en) | 2007-03-29 | 2013-08-27 | Micron Technology, Inc. | Manufacturing process for zero-capacitor random access memory circuits |
| US8064274B2 (en) | 2007-05-30 | 2011-11-22 | Micron Technology, Inc. | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same |
| US8085594B2 (en) | 2007-06-01 | 2011-12-27 | Micron Technology, Inc. | Reading technique for memory cell with electrically floating body transistor |
| KR100885784B1 (ko) * | 2007-08-08 | 2009-02-26 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치의 소프트 프로그램 방법 |
| US8369155B2 (en) * | 2007-08-08 | 2013-02-05 | Hynix Semiconductor Inc. | Operating method in a non-volatile memory device |
| WO2009039169A1 (en) | 2007-09-17 | 2009-03-26 | Innovative Silicon S.A. | Refreshing data of memory cells with electrically floating body transistors |
| US8536628B2 (en) | 2007-11-29 | 2013-09-17 | Micron Technology, Inc. | Integrated circuit having memory cell array including barriers, and method of manufacturing same |
| US8349662B2 (en) | 2007-12-11 | 2013-01-08 | Micron Technology, Inc. | Integrated circuit having memory cell array, and method of manufacturing same |
| JP5135608B2 (ja) * | 2007-12-27 | 2013-02-06 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US8773933B2 (en) | 2012-03-16 | 2014-07-08 | Micron Technology, Inc. | Techniques for accessing memory cells |
| US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
| US8189376B2 (en) | 2008-02-08 | 2012-05-29 | Micron Technology, Inc. | Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same |
| JP5194302B2 (ja) * | 2008-02-20 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | 半導体信号処理装置 |
| US7957206B2 (en) | 2008-04-04 | 2011-06-07 | Micron Technology, Inc. | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same |
| US7947543B2 (en) | 2008-09-25 | 2011-05-24 | Micron Technology, Inc. | Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation |
| US7933140B2 (en) | 2008-10-02 | 2011-04-26 | Micron Technology, Inc. | Techniques for reducing a voltage swing |
| US7924630B2 (en) | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
| US8223574B2 (en) * | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
| US8213226B2 (en) | 2008-12-05 | 2012-07-03 | Micron Technology, Inc. | Vertical transistor memory cell and array |
| US8319294B2 (en) | 2009-02-18 | 2012-11-27 | Micron Technology, Inc. | Techniques for providing a source line plane |
| US8710566B2 (en) | 2009-03-04 | 2014-04-29 | Micron Technology, Inc. | Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device |
| US8748959B2 (en) | 2009-03-31 | 2014-06-10 | Micron Technology, Inc. | Semiconductor memory device |
| US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
| US8508994B2 (en) | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
| US8498157B2 (en) | 2009-05-22 | 2013-07-30 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8537610B2 (en) | 2009-07-10 | 2013-09-17 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9076543B2 (en) | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8199595B2 (en) | 2009-09-04 | 2012-06-12 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8174881B2 (en) | 2009-11-24 | 2012-05-08 | Micron Technology, Inc. | Techniques for reducing disturbance in a semiconductor device |
| CN102598140A (zh) | 2009-12-04 | 2012-07-18 | 拉姆伯斯公司 | 支持低存储器单元电容的dram读出放大器 |
| US8310893B2 (en) | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
| US8416636B2 (en) | 2010-02-12 | 2013-04-09 | Micron Technology, Inc. | Techniques for controlling a semiconductor memory device |
| US9922981B2 (en) | 2010-03-02 | 2018-03-20 | Zeno Semiconductor, Inc. | Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making |
| US10461084B2 (en) | 2010-03-02 | 2019-10-29 | Zeno Semiconductor, Inc. | Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making |
| US8576631B2 (en) | 2010-03-04 | 2013-11-05 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8411513B2 (en) | 2010-03-04 | 2013-04-02 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device having hierarchical bit lines |
| US8369177B2 (en) | 2010-03-05 | 2013-02-05 | Micron Technology, Inc. | Techniques for reading from and/or writing to a semiconductor memory device |
| WO2011115893A2 (en) | 2010-03-15 | 2011-09-22 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US8411524B2 (en) | 2010-05-06 | 2013-04-02 | Micron Technology, Inc. | Techniques for refreshing a semiconductor memory device |
| US8531878B2 (en) | 2011-05-17 | 2013-09-10 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9559216B2 (en) | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
| US9029922B2 (en) | 2013-03-09 | 2015-05-12 | Zeno Semiconductor, Inc. | Memory device comprising electrically floating body transistor |
| US9275723B2 (en) | 2013-04-10 | 2016-03-01 | Zeno Semiconductor, Inc. | Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers |
| US9368625B2 (en) | 2013-05-01 | 2016-06-14 | Zeno Semiconductor, Inc. | NAND string utilizing floating body memory cell |
| US11169726B2 (en) * | 2018-09-13 | 2021-11-09 | Toshiba Memory Corporation | Pool-level storage management |
| US11062763B2 (en) * | 2019-04-09 | 2021-07-13 | Micron Technology, Inc. | Memory array with multiplexed digit lines |
| US20240407151A1 (en) * | 2023-05-30 | 2024-12-05 | Macronix International Co., Ltd. | Memory cell circuit, memory cell array structure and manufacturing method thereof |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10255487A (ja) * | 1997-03-10 | 1998-09-25 | Fujitsu Ltd | 半導体メモリ装置 |
| TW448611B (en) * | 1999-05-21 | 2001-08-01 | Ibm | Method and apparatus for fast SOI based amplifier |
| JP3940544B2 (ja) * | 2000-04-27 | 2007-07-04 | 株式会社東芝 | 不揮発性半導体メモリのベリファイ方法 |
| JP4032039B2 (ja) | 2004-04-06 | 2008-01-16 | 株式会社東芝 | 半導体記憶装置 |
| JP4110115B2 (ja) * | 2004-04-15 | 2008-07-02 | 株式会社東芝 | 半導体記憶装置 |
| JP4149961B2 (ja) | 2004-05-20 | 2008-09-17 | 株式会社東芝 | 半導体記憶装置 |
| CN1965404B (zh) * | 2004-06-09 | 2010-05-26 | 株式会社瑞萨科技 | 半导体存储装置 |
| JP2006073055A (ja) | 2004-08-31 | 2006-03-16 | Toshiba Corp | 半導体記憶装置 |
| US7764540B2 (en) * | 2006-03-01 | 2010-07-27 | Renesas Technology Corp. | Semiconductor memory device |
| JP4406413B2 (ja) * | 2006-04-18 | 2010-01-27 | 株式会社東芝 | 半導体記憶装置及びその読み出し方法 |
| JP4899751B2 (ja) * | 2006-09-27 | 2012-03-21 | 富士通セミコンダクター株式会社 | 半導体メモリおよび半導体メモリの試験方法 |
-
2006
- 2006-05-11 JP JP2006132895A patent/JP5068035B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-08 US US11/797,804 patent/US7652927B2/en active Active
- 2007-05-11 CN CNA2007101029134A patent/CN101071629A/zh active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169712A (zh) * | 2010-02-26 | 2011-08-31 | 海力士半导体有限公司 | 半导体存储器件 |
| CN104733037A (zh) * | 2015-03-27 | 2015-06-24 | 西安华芯半导体有限公司 | 一种控制字线泄放电流的装置 |
| CN104733037B (zh) * | 2015-03-27 | 2018-10-16 | 西安紫光国芯半导体有限公司 | 一种控制位线泄放电流的装置 |
| CN109903790A (zh) * | 2017-12-11 | 2019-06-18 | 旺宏电子股份有限公司 | 存储器装置及其操作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070263466A1 (en) | 2007-11-15 |
| JP5068035B2 (ja) | 2012-11-07 |
| JP2007305231A (ja) | 2007-11-22 |
| US7652927B2 (en) | 2010-01-26 |
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