4486 1 經濟部智慧財產局員工消费合作社印製 Α7 Β7 五、發明說明（） 發明领域： 本發明關係絕緣層上有矽（SOI)技術。更明確地說， 本發明關係於電路拓樸，其涉及SOI為主電路元件。更明 白地說’本發明關係於SOI為主放大器的反應時間改良· 發明背景： 絕緣層上有矽（SOI)類薄膜電晶體包含一主動區（源/ 汲極區），形成於一形成在半導體基材上之丰導體層上， 絕緣薄形成在半導髏基材下1因為主動區域係與半導體基 材絕緣’所以SOI類型薄膜電晶體係特徵在於主動區域之 接面電容係特別地小，而允許高速及低功率消耗之操作。 當SOI電晶體之鳢區域浮動時，主體之各種電壓位準 影響電晶體導通電壓。因為電晶體之導通電壓為電路資料 狀態之前一歷史之函數’所以例如感應放大器之應用效能 被降低。影黎電晶體導通電壓之各種電壓上下變化，而不 是保持固定。因此，操作之預測性變成—問題•當SOI電 晶艘之體電盤位準設定至地時，或vDD時，SOI電晶禮之 速度優點被消除，因為s 01電晶體臨限電壓係降低至醴裝 置之臨限電壓。 發明目的及概诚： 於需要例外狀態轉換時間及利用soi技術之電路 中，反應及狀態轉換時間之可預測性可以藉由將差動檢入 感應電晶體之主體電壓位準綁在差動資料輸入上而加以 ί琦先Mtt背面之;i意事項再填寫本頁) ^ -----II — 訂--— 1 — !線 —. 1 27Γ 衣紙張尺度適用中國困家標準(CNS>A4現格（210 χ 297公« )------- 44861 1 A7 B7 五、發明說明（) 最佳化》用於差動輸入感應電晶體之電晶體導通電壓係可 以預測，並藉由將差動輸入感應電晶體綁在其預充電輸入 而於速度上取得加強效能。如此，體電壓跟隨在電路輸入 電壓信號後，該電壓信號加速了差動輪入感應電晶體之反 應時間》 本發明之新穎特性係揭示於隨附之申請專利範面 中。然而，本發明本身，及用途較佳模式與其目的及優點 將參考以下例示實施例之詳細說明，配合上附圓而作最佳 了解，於圈式中： 置式簡簞說明： 第〖圖為於先前技藝中所知之感應故大器之電路圖； 第2圏為依據本發明之一較佳實施例之感應放大器電路； 第3圈為描述先前技藝差動感應放大器之另一實施例之電 路圖；及 第4圈為依據本發明之一較佳實施例之感應放大器電路。 (請先閲讀背面之注4事項再填寫本頁) 經濟部智慧財產局貝工消费合作社印製 凰號對照說明： 100 差動感應放大器電路 200 差動感應放大器 300 差動感應放大器電路 400 差動感應放大器電 N1 N型CMOS電晶體 N2 N型CMOS電晶雅 N3 N型CMOS電晶體 N4 電晶禮 N5 電晶體 P1 電晶髏 P2 電晶雉 P3 電晶體4486 1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention () Field of the invention: The invention has silicon (SOI) technology on the insulation layer. More specifically, the present invention relates to circuit topology, which involves SOI as the main circuit element. To put it more clearly, 'The present invention relates to the improvement of the response time of the SOI main amplifier. BACKGROUND OF THE INVENTION: There is a silicon (SOI) thin film transistor on the insulating layer, which includes an active region (source / drain region). The insulating layer is formed on the semiconductor substrate with a thin insulating layer under the semiconductor substrate. Because the active area is insulated from the semiconductor substrate, the SOI type thin film transistor system is characterized by a particularly small junction capacitance in the active area. While allowing high speed and low power consumption operation. When the 鳢 region of the SOI transistor is floating, various voltage levels of the main body affect the on-voltage of the transistor. Because the on-voltage of the transistor is a function of the history before the state of the circuit's data, the application efficiency of, for example, an inductive amplifier is reduced. The various voltages of the ONLE crystal's on-state voltage change up and down instead of staying fixed. Therefore, the predictability of operation becomes a problem. • When the volume level of the SOI transistor is set to ground, or vDD, the speed advantage of the SOI transistor is eliminated because the threshold voltage of the s 01 transistor is reduced. Threshold voltage to the device. Purpose of the invention and sincerity: In circuits that require exceptional state transition time and use SOI technology, the predictability of the response and state transition time can be tied to the differential data by detecting the main voltage level of the differential into the induction transistor Enter it and put it on the back of Mtt; I will fill in this page if necessary.) ^ ----- II — Order --- 1 —! Line —. 1 27Γ Applicable to Chinese standards (CNS >) A4 is now (210 χ 297 male «) ------- 44861 1 A7 B7 V. Description of the invention () Optimization" The on-voltage of the transistor used for differential input induction transistor can be predicted and borrowed Enhanced performance in speed by tying the differential input induction transistor to its pre-charge input. In this way, the body voltage follows the circuit's input voltage signal, which accelerates the response time of the differential wheel into the induction transistor. The novel characteristics of the invention are disclosed in the accompanying patent application. However, the invention itself, and the preferred mode of use, and its purpose and advantages will be best understood with reference to the detailed description of the exemplified embodiments below, with the attached circle In circle Middle: Brief description of the installation style: The first diagram is a circuit diagram of an inductive amplifier known in the prior art; the second diagram is an induction amplifier circuit according to a preferred embodiment of the present invention; the third circle is to describe the previous technique The circuit diagram of another embodiment of the differential sense amplifier; and the fourth circle is a sense amplifier circuit according to a preferred embodiment of the present invention. (Please read Note 4 on the back before filling out this page.) Intellectual Property Bureau, Ministry of Economic Affairs Printed by Peiger Consumer Cooperative, the description of the Phoenix is 100 Differential inductive amplifier circuit 200 Differential inductive amplifier 300 Differential inductive amplifier circuit 400 Differential inductive amplifier N1 N-type CMOS transistor N2 N-type CMOS transistor N3 N-type CMOS Transistor N4 Transistor N5 Transistor P1 Transistor P2 Transistor P3 Transistor
第3T 本紙張尺度適用中困國家標準i；CNS>A4規格（210 X 297公釐） 4486 1 經濟部智慧財產局βκ工消费合作社印製 A7 B7 五、發明說明（） P4 電晶體 - J1 接面 J2 接面 發明詳細說明： 第1圖例示先前技藝之感應故大器之電路闽。差動感 應放大器電路100包含三個N型CMOS電晶體Nl，N2, 及N3«電晶體N1及N2之源極係連接至第三n-MOS電晶 體N3之没極。電晶« N3之閘極係連接至感應致能輸入 SENB ’及電晶雄N3之源極係連接至地端a電晶體N1之 汲極係連接至電晶體P1之汲極，及電晶體P1及N1之閘 極係綁在一起。電晶體P1之源極係連接至電壓Vdc^同 樣地，電晶體N2之汲極係連接至電晶體P2之汲極，及電 晶體P2及N2之閘極係綁在一起。電晶體P2之源極同時 連接至輸入電壓VDD。 差動感應放大器電路100同時包含兩反相器II及 12。反相器II之輸入係連接至電晶體Ρ2及Ν2之閘極， 並至電晶體Ρ1及Ν1之汲極。反相器12之輸入係連接至 電晶體Ρ1及Ν〗之閘極及電晶體Ρ2及Ν2之汲極•位元 線電壓BL係出現在反相器II之輸入，及位元線電壓BL_B 係出現在反相器12之輸入。 回到電晶體N1及N2，注意N1之電晶體主體係連接 至地端於接面Π。同樣地，N2之電晶禮主鳢係連接至地 端於接面J2·兩電晶體N1及N2之狀態保持於地端（或 低），而無關於位元線BL及BL_B上之信號狀態（不論高或 第4貫 本紙張尺度適用中國國家標準<CNS)A4規格（210 * 297公* ) (請先Mi»背面之注意事項再填窝本頁)3T This paper standard applies to the national standard for hardship i; CNS > A4 specification (210 X 297 mm) 4486 1 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs βκ 工 消费 consuming cooperative A7 B7 V. Description of invention () P4 transistor-J1 connector The detailed description of the invention of connection J2 is as follows: The first figure illustrates the circuit of the prior art inductive amplifier. The differential inductive amplifier circuit 100 includes three N-type CMOS transistors N1, N2, and N3 «sources of the transistors N1 and N2 are connected to the terminals of the third n-MOS transistor N3. The transistor «N3's gate is connected to the sensing enable input SENB 'and the transistor N3's source is connected to the ground terminal a. The transistor N1's drain is connected to the transistor P1's drain, and the transistor P1 and The gates of N1 are tied together. The source of transistor P1 is connected to the voltage Vdc ^ Similarly, the drain of transistor N2 is connected to the drain of transistor P2, and the gates of transistors P2 and N2 are tied together. The source of transistor P2 is also connected to the input voltage VDD. The differential sense amplifier circuit 100 includes two inverters II and 12 at the same time. The input of inverter II is connected to the gates of transistors P2 and N2, and to the drains of transistors P1 and N1. The input of inverter 12 is connected to the gates of transistors P1 and N, and the drains of transistors P2 and N2. The bit line voltage BL appears at the input of inverter II, and the bit line voltage BL_B is Appears at the input of inverter 12. Returning to transistors N1 and N2, note that the transistor main system of N1 is connected to the ground terminal at the interface Π. Similarly, the main transistor of N2 is connected to the ground and the junction J2. The state of the two transistors N1 and N2 is maintained at the ground (or low), regardless of the signal state on the bit lines BL and BL_B. (Regardless of the height of the paper or the 4th paper, the Chinese national standard < CNS) A4 size (210 * 297 male *) (please note Mi »the precautions on the back before filling this page)
^ί — 1 — ί—訂 J I I I I 11 I -n n n B— n 1« I* n IV . 448611 A7 B7 五、發明說明（） 低或者，電晶體N1及N2之主鳢可以連接至電壓Vdd(未 示出）。 至於差動感應放大器電路100之操作，電晶踵1^1及 N2感應到在輸入線BL及BL_B之差動位元線電壓《於實 際上’一輸入電壓線係為另一個之補數。電晶鱧P1及P2 作動為用於放大器輸入級之低拉升裝置β電晶體N3係作 用以致能感應放大器，及差動輸入係被創造於位元線輪入 BL及位元線輸入BL_B之間》來自差動感應放大器 之輸出信號係進一步被反相級Π及12所故大。來自線BL 及BL_B之位元線電壓經由反相級II及12被反相輸出並 放大信號，成為輸出BL_B及輸出B。雖然此放大器可如 所期待動作，但差動感應放大器100之效能係較想要者為 慢。 於描繪於第1蹰之差動感應放大電路100之第二變化 例（未示出）中，電晶體N1及N2之主體被允許流動。即’ 相反於連接電晶體N1經接面Π至地端，主體仍保持與地 端隔絕。同樣地，電晶體N2之主體不是經由接面J2連接 至地端’而是浮置於地端上。藉由允許電晶體Nl，N2之 主鳢浮置，有以下缺點發生·當位元線之一，不是線BL 就是BL_B ’切換相關路徑之主體，則電晶體N1或N2具 有一較低電位，因此，發生一電晶禮導通電壓失配。當電 晶體下，電晶髏N1或N2未綁至地端，則電晶體主禮噱壓 浮置於各種電壓位準，其影響電晶體導通電壓VT。很多 應用並不能容許電晶體導通電賡為前一電路歷史之函 第5頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <锖先閲讀背面之注意事項再瑱寫本頁> -----I丨丨訂------I--線丨- 經濟部智慧財產局員工消费合作社印敦 -I ϋ n I If n n 1 - 44861 1 A7 五、發明說明（） 數•問題之發生係因為導通電壓係為舊資料狀態所影響。 因此’電晶體反應之可預期性變成一問題。 至於’另一差動感應放大器100之操作，位元線輸入 BL及BL_B係被預充電至高，及感應放大器致能SENB為 關係或低》反相輸出輸出B及輸出B_B為低或關閉》電 晶體N1及N2為導通，及電晶體P1及P2為關閉》於位 元輸入線BL及BL_B間，足夠電位差被發展超出雜訊臨 限值之計時期間後，感應放大致能SENB為高。於位元輪 入線BL及BL_B上之資料造成一線，即位元输入線保持 為高’而其補數，位元輸入線BL_B變為低，而闞閉電晶 體N2，同時導通電晶體P2。於此例子中，電晶體N1保 持導通及電晶體P1保持關閉，因為輸入線BL保持為高》 因此，叉鏈栓鎖係被觸發，捕捉位元線值。這處理每遇期 均重覆β 經濟部智慧財產局員工消费合作社印製 依據本發明之較佳實施例，對於此所述之解答係藉由 提供電晶體之體區來自差動輸入感應電晶體至施加至其 閘極之控制資料輸入信號之連接。這允許體電壓跟隨電路 輸入電壓並協助於感應放大器電路中之放大作用，因而加 速其反應時間並同時建立已知被控制參考雅電壓，使得電 晶禮反應或動作變成可預測。雖然，本放大器可以如想要 的動作，但差動感應放大器1〇〇之效能係較想要的為慢》 第2圖例示依據本發明之較佳實施例之差動感應放大 器電路。差動感應放大器200係基本上相同於描述於第1 圖中之差動感應放大器100»但是，相反於連接相關電晶 第6Τ 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐) 4486 1 1 A7 B7 經濟部智慧財產局貝工消费合作社印數 五、發明說明（> 體主髏至地端之電晶體N1及N2之接面Π及J2的是，電 晶體N1之主體係經由接面J1連接至位元線電壓輸入 BL—B及電晶體N2之主體係經由接面JT2連接至位元線電 壓輸入BL <· 因此’差動感應放大器200係基本上不同於先前技藝 在於差動感應電晶體之體電壓係設定至電晶體輸入電壓 信號，並未設定至地端或一固定Vdd電壓。依據本發明之 一較佳實施例，電晶體Ν1及Ν2之主體係被綁於其閘極， 其係啟始分別被在位元線BL_B及位元線BL上之預充電 所預充電為高。這使得裝置於一快速狀或低VTe於一些 時段以允許於位元線間之足夠差動電壓後，感應故大器輸 入SENB導通變為高。 於電路操作中*假設位元輸入線BL_B電壓大約低於 位元輸入線BL200毫伏。因此，電晶體N!之主禮係為低 電位或較高VT *及電晶體N 1之閘極係於較電晶體N2閘 極為低之電位。電晶體N2之閘極係為全滿或高，及電晶 體N2之主禮同時為滿，使得電晶體N2為快速狀態。上述 组髏閘電位將較快關閉電晶體N1及較快導通電晶體N2 , 使得栓鎖結構快速捕捉位元值。 第3圔為一電路囷，描繪先前技藝差動感應放大器之 另一實施例。差動感應放大器3 00包含五個N-型CMOS 電晶體*電晶體N1及N2之源極係連接至電晶鱧ΝΓ3及N4 之汲極》電晶體N3及N4之源極係連接至第五個N-M0S 電晶體N5。電晶雔N5之源極係連接至感應致能輪入 第7貰 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公爱） n n ϋ n ί *1 .^1 n I I I n n I ϋ )aJI ϋ I ϋ n 1 n I I 線！ (請先»讀背面之注意Ϋ項再填寫本頁)^ ί — 1 — ί—Order JIIII 11 I -nnn B—n 1 «I * n IV. 448611 A7 B7 V. Description of the invention () Low or, the main terminals of the transistors N1 and N2 can be connected to the voltage Vdd (not Shows). As for the operation of the differential inductive amplifier circuit 100, the transistors 1 ^ 1 and N2 sense the differential bit line voltages "in actuality" on the input lines BL and BL_B. One input voltage line is the complement of the other. Transistors 1 P1 and P2 act as low-lift devices for the input stage of the amplifier. The β-transistor N3 system functions to enable the inductive amplifier, and the differential input system is created in the bit line input BL and bit line input BL_B. The output signal from the time difference amplifier is further increased by the inverting stages Π and 12. The bit line voltages from the lines BL and BL_B are inverted and output via the inverting stages II and 12 and amplify the signals to become the outputs BL_B and B. Although this amplifier can operate as expected, the performance of the differential inductive amplifier 100 is slower than desired. In a second variation (not shown) of the differential induction amplifier circuit 100 depicted in the first frame, the bodies of the transistors N1 and N2 are allowed to flow. That is, 'as opposed to connecting the transistor N1 to the ground via the junction surface Π, the main body remains isolated from the ground. Similarly, the body of the transistor N2 is not connected to the ground terminal 'via the junction J2, but floats on the ground terminal. By allowing the main transistors N1 and N2 to float, the following disadvantages occur: When one of the bit lines, either line BL or BL_B, switches the subject of the relevant path, the transistor N1 or N2 has a lower potential, Therefore, a mismatch of the on-state voltage of the transistor occurs. When the transistor N1 or N2 is not tied to the ground under the transistor, the transistor is floated at various voltage levels, which affects the transistor's on-voltage VT. Many applications do not allow the transistor to be energized. It is a letter from the previous circuit history. Page 5 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) < 锖 Read the precautions on the back before reading 瑱Write this page > ----- I 丨 丨 Order ------ I--line 丨-Consumer Cooperative, Indun, Intellectual Property Bureau, Ministry of Economic Affairs-I 印 n I If nn 1-44861 1 A7 V. Description of the invention () The number of problems occurs because the on-voltage is affected by the old data state. Therefore the predictability of the 'transistor reaction becomes a problem. As for the operation of another differential inductive amplifier 100, the bit line inputs BL and BL_B are precharged to high, and the inductive amplifier enables SENB to be low or high. "Inverting output output B and output B_B are low or closed." The crystals N1 and N2 are on, and the transistors P1 and P2 are off. Between the bit input lines BL and BL_B, when the sufficient potential difference is developed beyond the timing period of the noise threshold, the inductive amplification enables SENB to be high. The data on the bit wheel input lines BL and BL_B create a line, that is, the bit input line remains high 'and its complement, the bit input line BL_B goes low, and the electric crystal N2 is closed, and the crystal P2 is turned on at the same time. In this example, transistor N1 remains on and transistor P1 remains off because the input line BL remains high. Therefore, the fork chain latch system is triggered to capture the bit line value. This process repeats every beta period. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a preferred embodiment according to the present invention. The solution to this is based on the differential input induction transistor provided by the body of the transistor. Connection to a control data input signal applied to its gate. This allows the body voltage to follow the input voltage of the circuit and assist the amplification in the inductive amplifier circuit, thereby speeding up its response time and simultaneously establishing a known controlled reference voltage, making the crystallographic response or action predictable. Although the amplifier can operate as desired, the performance of the differential inductive amplifier 100 is slower than desired. Figure 2 illustrates a differential inductive amplifier circuit according to a preferred embodiment of the present invention. The differential inductive amplifier 200 is basically the same as the differential inductive amplifier 100 described in the first picture. However, it is opposite to the connection of the relevant transistor 6T. This paper size applies to the Chinese national standard (CNS> A4 size (210 X 297 mm) 4486 1 1 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 5. Description of the invention (> The junctions of the transistors N1 and N2 from the main body to the ground, and J2 are The main system is connected to the bit line voltage input BL-B through the junction J1 and the transistor N2 is connected to the bit line voltage input BL through the junction JT2. Therefore, the 'differential induction amplifier 200 series is basically different from The prior art is that the body voltage of the differential induction transistor is set to the transistor input voltage signal and is not set to ground or a fixed Vdd voltage. According to a preferred embodiment of the present invention, the main system of the transistors N1 and N2 Tied to its gate, it was initially precharged high by pre-charging on bit line BL_B and bit line BL respectively. This allows the device to be in a fast state or low VTe for some periods to allow it to be in place Sufficient differential voltage between element wires After that, the inductive amplifier input SENB is turned on. In the circuit operation * Assuming that the bit input line BL_B voltage is approximately lower than the bit input line BL200 millivolts. Therefore, the main gift of the transistor N! Is a low potential or The higher VT * and the transistor N1's gate are at a much lower potential than the transistor N2's gate. The transistor N2's gate is fully or high, and the transistor N2's main ceremony is full at the same time, making the The crystal N2 is in a fast state. The cross-gate potential of the above group will turn off the transistor N1 and the conducting crystal N2 more quickly, so that the latching structure quickly captures the bit value. The third is a circuit, depicting the differential sensing of the previous technology. Another embodiment of the amplifier. The differential sense amplifier 300 includes five N-type CMOS transistors. The sources of the transistors N1 and N2 are connected to the drains of the transistors NΓ3 and N4. The transistors N3 and N4 The source is connected to the fifth N-M0S transistor N5. The source of the transistor N5 is connected to the induction enable wheel 7th. This paper size applies to China National Standard (CNS) A4 (210 X 297 male) Love) nn ϋ n ί * 1. ^ 1 n III nn I ϋ) aJI ϋ I ϋ n 1 n II line! (Please read it first » Note Ϋ the item and then fill in the page)
448 6 U A7 B7 經濟部智慧財產局藥工消費合作杜印製 五、發明說明（） SENB，及電晶體N5之源極係連接至地端》電晶體N1之 汲極係連接至電晶體·Ρ1及Ρ3之汲極，及電晶體Ρ1及Ν1 之閘極係綁在一起。電晶體Ρ1及Ρ3之源極係連接至電壓 Vdd。 差動感應放大器電路300之另一側，電晶體N2之汲 極係連接至電晶體P2及P4之汲極，及電晶體P2及N2 係綁在一起》電晶體P2及P4之源極係連接至輸入電壓 Vdd。 差動感應故大器t路300同時包含兩反相器級II及 12。反相級II之輸入係連接至電晶體P2及N2之閘極及 電晶體PI，P3及N1之汲極。反相級12之輸入係連接至 電晶體P1及N1之閘極，及電晶體P2，P4及N2之汲極。 位元線電壓係出現在線BL至電晶體N3之閘極。位元線 電壓BL_B係出現在電晶體N4之閘極。感應致能輸入 SENB係連接至電晶體N5，P3及P4之閘極。 回來參考電晶鳢N〖及N2，注意NI之電晶體主鱧係 於接面J1連接至地端。同樣地，N2之電晶體主體係藉由 接面J2連接至地端。電晶體N1及N2之狀態係保持地端， 而無閣於位元線BL及BL_B上之信號狀態。電晶體N1及 N2之主雅或者可以連接至電壓Vdd(未示出p電晶體N3 及N4之主體係同時分別經由接面J3及J4連接至地端《 於描繪於第3圈中之差動感應放大器電路3 00之第二 變化例（未示出），電晶體Nl，N2，N3，及N4之主雅係允 許流動》即，不是於接點J1，J2，J3及J4將電晶鳢N1， 第8頁 (請先閲讀背面之注意事項再填寫本頁> 本紙張尺度適用中國國家標準j；CNS〉A4規格（21〇 χ 297公釐）448 6 U A7 B7 Printed by the pharmaceutical industry and consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () SENB, and the source of transistor N5 is connected to the ground. The drain of transistor N1 is connected to the transistor. The drains of P1 and P3 and the gates of transistors P1 and N1 are tied together. The sources of the transistors P1 and P3 are connected to the voltage Vdd. On the other side of the differential sense amplifier circuit 300, the drain of transistor N2 is connected to the drains of transistors P2 and P4, and the transistors P2 and N2 are tied together. The sources of transistors P2 and P4 are connected. To the input voltage Vdd. The differential circuit 300 includes two inverter stages II and 12 at the same time. The input of the inverting stage II is connected to the gates of transistors P2 and N2 and the drains of transistors PI, P3 and N1. The input of the inverting stage 12 is connected to the gates of transistors P1 and N1, and the drains of transistors P2, P4, and N2. The bit line voltage appears at the gate from line BL to transistor N3. The bit line voltage BL_B appears at the gate of transistor N4. The sensing enable input SENB is connected to the gates of transistors N5, P3 and P4. Refer back to transistor N 鳢 and N2. Note that the main transistor of NI is connected to the ground terminal J1. Similarly, the main transistor N2 system is connected to the ground terminal through the junction J2. The states of the transistors N1 and N2 are kept at the ground, and there is no signal state on the bit lines BL and BL_B. The masters of transistors N1 and N2 may be connected to the voltage Vdd (the main system of p transistors N3 and N4 is not connected to the ground at the same time through the junctions J3 and J4, respectively. The second variation of the sense amplifier circuit 3 00 (not shown), the main circuits of the transistors N1, N2, N3, and N4 are allowed to flow. N1, page 8 (Please read the notes on the back before filling in this page> This paper size applies to Chinese national standard j; CNS> A4 specification (21〇χ 297 mm)
• I I I I I I n )SJ I I I n I —II - 1— - - I - - - f - - 1 I I - u [ n t ] n - I A7 B7 五、發明說明（ 經濟部智慧財產局貝工消费合作社印製 N2’N3及N4連接至地端，而是電晶體主體保持與地端挹 緣。 於操作中’感應放大器致能SENB於差動感應放大器 電路300 t，敌始時係為關閉或^電晶體P3及μ係為 導通，允許vdd預充電電晶鱧p丨，p2，N 1及N3之閘極。 預充電使得输出B及B_B由反相器η及π至保持為低》 電晶想N1及N3之閘極同時具有短電壓Vdd之作用，以經 由開通電晶髖Μ 1及N2預充電電晶體N3及N4之源極。 於位元輸入線BL及BL_B間之足夠電位差發展超出雜訊 臨限之時問段後*感應放大器致能SENB變為高"於位元 輸入線BL及BL_B上之資料使得一線，即位元輸入線Bl 保持為高，同時，其補數，即位元輸入線BL_B變為低， 使得電晶體N4關閉。於此時，電晶體N3保持導通。關閉 電晶禮N4之動作’具有保持電晶體pi及Ni預充電位準 之作用，同時’導通電晶體N5具有將電晶鳢N1及 極上之預充電位準經由電晶體1<5排至地端之作用。一旦 電晶艘N1及N3上之預充電被消散，則因為於電晶艟p2 及N2閘極上之預充電已經同樣被經由電晶體Ni，N3最 後經電晶體N5消散，所以電晶體p2導通及電晶體N2闞 閉。因此’交叉稱合栓鎖被觸動，捕捉了位元線值β這些 處理每週期均重覆。換句話說’於感應放大器致能senb 變為高後’差動感應放大器電路3 〇〇作動像差動感應放大 電路10(^該處理每週期重覆a 第4圖例示依據本發明較佳實施例之差動感應放大電 第9頁 表紙張尺度適用中國國家標準(CNS)A4規格(210 (请先閲讀背面之注意事項再填窝本頁) * it n n n It• IIIIII n) SJ III n I —II-1—--I---f--1 II-u [nt] n-I A7 B7 V. Description of the invention N2'N3 and N4 are connected to the ground, but the body of the transistor is kept at the edge of the ground. In operation, the 'sense amplifier' enables the SENB to be 300 t in the differential sense amplifier circuit. The enemy was initially turned off or the transistor P3 and μ are on, allowing vdd to precharge the gates of the transistors 鳢 p 丨, p2, N1, and N3. Precharging makes the outputs B and B_B from the inverters η and π to low. And the gate of N3 has the function of short voltage Vdd at the same time to pre-charge the sources of transistors N3 and N4 by turning on transistors M1 and N2. Sufficient potential difference between bit input lines BL and BL_B develops beyond noise After the threshold is reached, the sense amplifier enables SENB to go high. The data on the bit input lines BL and BL_B makes the first line, that is, the bit input line Bl remains high, and at the same time, its complement, that is, the bit input Line BL_B goes low, causing transistor N4 to turn off. At this time, transistor N3 remains on. Turning off transistor N4 The action 'has the role of maintaining the pre-charge level of the transistor pi and Ni, and at the same time, the conducting transistor N5 has the role of rowing the transistor N1 and the pre-charge level on the pole to the ground via the transistor 1 < 5. The pre-charges on the wafers N1 and N3 are dissipated, because the pre-charges on the transistors 艟 p2 and N2 have also been dissipated through the transistors Ni, N3 and finally the transistors N5, so the transistor p2 is turned on and the transistor N2 is closed. Therefore, the 'cross-lock latch is touched, and the bit line value β is captured. These processes are repeated every cycle. In other words,' after the sense amplifier enables senb to become high ', the differential sense amplifier circuit 3 〇〇 Actuating the differential induction amplifier circuit 10 (^ This process repeats a every cycle. Figure 4 illustrates the differential induction amplifier according to the preferred embodiment of the present invention. Page 9 The paper dimensions are applicable to the Chinese National Standard (CNS) A4. Specifications (210 (Please read the notes on the back before filling in this page) * it nnn It
a— Kt I I 線— 44861 A7 B7 五、發明說明（） 路。差動感應放大電路400係基本上相同於燴於第3圖中 之電路》然而，相反於電晶體N1及N2之接面J1及J2連 接至相闞電晶體之主體至地端，電晶體N1之主髏係連接 至閘控制電壓，其於預充電狀態時為電壓Vdd。電晶雔N2 之主體係連接至其閘極控制電壓，其於預充電狀態也是電 壓Vdda再者’電晶想N3之主體係同時經由接面J3連接 至電晶體N1之閘控制電壓，其於預充電狀態是為電壓 Vd«r電晶體N4之主鳢係經由接面J4連接至電晶« N2之 閘控制電壓，其於預充電狀態是電壓Vdd。 因此，差動感應放大器400係基本上不同於先前技藝 者在於差動感應電晶體之主體電壓係被設定至電晶體輸 入電壓信號，其係至少開始時為預充電電壓Vdd。 依據本發明之一較佳實施例，電晶體Nl，N2，N3， N4之主體開始時被預充電電壓vdd經由電晶體P3及P4 加以預充電為高。這使得裝置於一快速狀態或一低νΤβ 於位元線間之足夠差動電壓之一些時段後，感應放大器 SENB反應於BL及BL_B間之位元輸入線差，而導通並變 為高。假設BL„B電壓大約200毫伏低於位元輸入線BL β 電晶體Ν3之閘極係滿或高，由位元資料線BL變為高及 電晶體N3之主體保持為高，因為電壓Vdd預充電’使得 電晶體N3於一很快狀態或低VT»因此，電晶體N3導通’ 完成經由電晶禮N5至地端之路徑》 隨著_經由電晶體N3至地端路徑之開故，於電晶嫌 P2及N2閘極上之預充電電壓Vdd消散至地端，及電晶艘a— Kt I I line— 44861 A7 B7 V. Description of the invention () Road. The differential induction amplifier circuit 400 is basically the same as the circuit immersed in Figure 3. However, instead of the junctions J1 and J2 of the transistors N1 and N2, the main body of the transistor is connected to the ground, and the transistor N1 The main skeleton is connected to the brake control voltage, which is the voltage Vdd in the precharge state. The main system of transistor N2 is connected to its gate control voltage, which is also the voltage Vdda in the pre-charged state, and the main system of transistor N3 is also connected to the gate control voltage of transistor N1 via junction J3. The precharge state is the gate control voltage of the transistor V4 with the voltage Vd «r connected to the transistor« N2 via the junction J4, which is the voltage Vdd in the precharge state. Therefore, the differential induction amplifier 400 is basically different from the prior art in that the main voltage of the differential induction transistor is set to the transistor input voltage signal, which is at least the precharge voltage Vdd at the beginning. According to a preferred embodiment of the present invention, the bodies of the transistors N1, N2, N3, and N4 are initially precharged by the precharge voltage vdd via the transistors P3 and P4 to be high. This makes the device in a fast state or a period of time with a low νΤβ enough differential voltage between the bit lines, the sense amplifier SENB reacts to the bit input line difference between BL and BL_B, and turns on and goes high. Assuming that the voltage of BL „B is about 200 millivolts lower than the bit input line BL β, the gate of the transistor N3 is full or high, the bit data line BL goes high and the body of the transistor N3 remains high because the voltage Vdd Pre-charging 'makes transistor N3 in a very fast state or low VT »Therefore, transistor N3 is turned on' to complete the path from transistor N5 to ground. With the opening of transistor N3 to ground, The pre-charge voltage Vdd on the transistor P2 and N2 gates dissipates to the ground, and the transistor
第10T 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） (請先閲讀背面之沒意事項再填窝本頁) 經濟部智慧財產局工消费合作杜印製10T This paper size applies Chinese national standard (CNS > A4 size (210 X 297 mm) (please read the unintentional matter on the back before filling in this page)) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs
· I I n n .1· I I . /' 1· n ϋ n 1 n n n 1 i> n n ϋ IK .^1 n n I 448 6 1 1 Α7 Β7 五、發明說明（） N2及N4主體上之預充電電壓Vdd也是如此1於電晶體N4 主體上之預充電電壓之消散使得電晶體N4之主體為低電 位’及高VT，使得電晶體N4較沒有電晶體主體被預充電 較快關閉。電晶體N4之閘極係同時也較電晶體N3之閘極 為低’因為電壓BL係較高於電壓BL_B。上述之體-閘極 電位組將較快關閉電晶體Ν3及較快導通電晶體Ν4，使得 電晶體Nl ’ Ν2，Ρ1及Ρ2之栓鎖結構快速捕捉位元值Β 應注意的是’本發明己經全動作差動感應蜂大器電路 加以描述，熟習於本技藝者可以了解的是本發明之處理可 以以各種電路拓樸加以執行。 本發明之說明只作為例示及說明用，而不限定包含或 限定本發明於所述之形式中。對於熟習於本技藝者而言， 各種修改及變化係明顯的。諸實施例係以最容易解釋本發 明應用之原理方式加以選擇及描述，以使得熟習於本技藝 者可以了解本發明可用於具不同修改之各種實施 <猜先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消费合作社印製 第11頁 本紙張尺度適用令國S家標準iCNS>A4規格（210 X 297公釐i· II nn .1 · II. / '1 · n ϋ n 1 nnn 1 i > nn ϋ IK. ^ 1 nn I 448 6 1 1 Α7 Β7 V. Description of the invention () Precharge voltage Vdd on N2 and N4 bodies The same is true. 1 The dissipation of the precharge voltage on the body of transistor N4 makes the body of transistor N4 a low potential and a high VT, so that transistor N4 is pre-charged off faster than no transistor body. The gate of transistor N4 is also lower than the gate of transistor N3 because the voltage BL is higher than the voltage BL_B. The aforementioned body-gate potential group will close the transistor N3 and the conduction transistor N4 faster, so that the latching structure of the transistor N1'N2, P1, and P2 will quickly capture the bit value B. It should be noted that the present invention The full-motion differential induction buzzer circuit has been described. Those skilled in the art can understand that the processing of the present invention can be performed with various circuit topologies. The description of the present invention is only for illustration and explanation, and is not limited to include or limit the present invention in the form described. For those skilled in the art, various modifications and changes are obvious. The embodiments are selected and described in a way that most easily explains the principles of the application of the present invention, so that those skilled in the art can understand that the present invention can be used for various implementations with different modifications < read the precautions on the back before filling in this Page> Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Page 11 This paper is applicable to national standards iCNS > A4 specifications (210 X 297 mm i