CN100530568C - Mos栅器件制造方法 - Google Patents

Mos栅器件制造方法 Download PDF

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Publication number
CN100530568C
CN100530568C CNB038106094A CN03810609A CN100530568C CN 100530568 C CN100530568 C CN 100530568C CN B038106094 A CNB038106094 A CN B038106094A CN 03810609 A CN03810609 A CN 03810609A CN 100530568 C CN100530568 C CN 100530568C
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CN
China
Prior art keywords
paster
source
grid
metal layer
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038106094A
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English (en)
Chinese (zh)
Other versions
CN1653602A (zh
Inventor
理查德·A·布朗夏尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Semiconductor Inc
Original Assignee
General Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/142,600 external-priority patent/US6710414B2/en
Priority claimed from US10/142,622 external-priority patent/US6861337B2/en
Application filed by General Semiconductor Inc filed Critical General Semiconductor Inc
Publication of CN1653602A publication Critical patent/CN1653602A/zh
Application granted granted Critical
Publication of CN100530568C publication Critical patent/CN100530568C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
CNB038106094A 2002-05-10 2003-05-09 Mos栅器件制造方法 Expired - Fee Related CN100530568C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/142,600 US6710414B2 (en) 2002-05-10 2002-05-10 Surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes
US10/142,622 US6861337B2 (en) 2002-05-10 2002-05-10 Method for using a surface geometry for a MOS-gated device in the manufacture of dice having different sizes
US10/142,622 2002-05-10
US10/142,600 2002-05-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN200910150498A Division CN101697349A (zh) 2002-05-10 2003-05-09 用于mos栅器件的表面几何结构

Publications (2)

Publication Number Publication Date
CN1653602A CN1653602A (zh) 2005-08-10
CN100530568C true CN100530568C (zh) 2009-08-19

Family

ID=29423049

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB038106094A Expired - Fee Related CN100530568C (zh) 2002-05-10 2003-05-09 Mos栅器件制造方法
CN200910150498A Pending CN101697349A (zh) 2002-05-10 2003-05-09 用于mos栅器件的表面几何结构

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN200910150498A Pending CN101697349A (zh) 2002-05-10 2003-05-09 用于mos栅器件的表面几何结构

Country Status (6)

Country Link
EP (1) EP1504467A1 (ja)
JP (1) JP4938236B2 (ja)
CN (2) CN100530568C (ja)
AU (1) AU2003241408A1 (ja)
TW (1) TWI268549B (ja)
WO (1) WO2003096406A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004048278B3 (de) * 2004-10-05 2006-06-01 X-Fab Semiconductor Foundries Ag Simulations- und/oder Layoutverfahren für Leistungstransistoren, die für unterschiedliche Leistungen ausgelegt sind
EP2308096A1 (en) * 2008-07-28 2011-04-13 Nxp B.V. Integrated circuit and method for manufacturing an integrated circuit
JP5742627B2 (ja) * 2011-09-26 2015-07-01 住友電気工業株式会社 半導体装置および半導体装置の製造方法
JP5630552B2 (ja) * 2013-10-15 2014-11-26 富士電機株式会社 炭化珪素半導体装置およびその製造方法
WO2017002368A1 (ja) * 2015-07-01 2017-01-05 パナソニックIpマネジメント株式会社 半導体装置
US11031343B2 (en) 2019-06-21 2021-06-08 International Business Machines Corporation Fins for enhanced die communication
EP3863065A1 (en) * 2020-02-04 2021-08-11 Infineon Technologies Austria AG Semiconductor die and method of manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
US5499124A (en) * 1990-12-31 1996-03-12 Vu; Duy-Phach Polysilicon transistors formed on an insulation layer which is adjacent to a liquid crystal material
GB9106720D0 (en) * 1991-03-28 1991-05-15 Secr Defence Large area liquid crystal displays
AU2546897A (en) * 1996-03-25 1997-10-17 Rainbow Displays, Inc. Tiled, flat-panel displays with color-correction capability
JP3276325B2 (ja) * 1996-11-28 2002-04-22 松下電器産業株式会社 半導体装置
JP2001352063A (ja) * 2000-06-09 2001-12-21 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP3597762B2 (ja) * 2000-07-24 2004-12-08 株式会社日立製作所 半導体集積回路及びその製造方法

Also Published As

Publication number Publication date
WO2003096406A1 (en) 2003-11-20
JP4938236B2 (ja) 2012-05-23
TW200403730A (en) 2004-03-01
EP1504467A1 (en) 2005-02-09
AU2003241408A1 (en) 2003-11-11
CN1653602A (zh) 2005-08-10
JP2005525701A (ja) 2005-08-25
CN101697349A (zh) 2010-04-21
TWI268549B (en) 2006-12-11

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C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090819

Termination date: 20100509