CN100495662C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN100495662C
CN100495662C CNB2005100994963A CN200510099496A CN100495662C CN 100495662 C CN100495662 C CN 100495662C CN B2005100994963 A CNB2005100994963 A CN B2005100994963A CN 200510099496 A CN200510099496 A CN 200510099496A CN 100495662 C CN100495662 C CN 100495662C
Authority
CN
China
Prior art keywords
impurity
semiconductor
semiconductor device
active area
decrystallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100994963A
Other languages
English (en)
Other versions
CN1841680A (zh
Inventor
宫下俊彦
铃木邦广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of CN1841680A publication Critical patent/CN1841680A/zh
Application granted granted Critical
Publication of CN100495662C publication Critical patent/CN100495662C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体器件及其制造方法，其中能够容易且可靠地实现沟道区域中的理想阶梯式分布，由此能同时抑制短沟道效应及防止迁移率下降。从半导体膜起将硅衬底非晶化到预定深度，并且在这种状态下引入将成为源极/漏极的杂质。然后激活杂质，并且通过低温固相外延再生长将非晶化的部分再结晶。由于低温固相外延再生长所需的处理温度在450℃-650℃范围内，因而能够抑制杂质热扩散到半导体膜，从而保持初始陡峭的阶梯式分布。

Description

半导体器件及其制造方法
相关申请的交叉参考
本申请基于并要求2005年3月30日提交的在先日本专利申请No.2005-099802的优先权，在此通过参考援引其全部内容。
技术领域
本发明涉及一种用于MOS晶体管等的半导体器件及其制造方法，并且尤其涉及一种适用于高性能CMOS晶体管等的半导体器件及其制造方法。
背景技术
近年来，对CMOS晶体管进一步微型化(miniaturization)的需求正不断增长，促使人们尽量缩短栅极长度来满足这种需求。然而，伴随着栅极长度的缩短产生称为短沟道效应的问题。因此，人们提出通过提高沟道区域内的杂质浓度来抑制短沟道效应的方法。但是，沟道区域内杂质浓度的提高会因杂质散射而导致载流子迁移率下降，从而阻碍了驱动电流的增大。因此，在试图缩短栅极长度时，抑制短沟道效应的需求和防止载流子迁移率下降的需求就呈互相制约(trade off)的关系。
为了解决上述问题，人们提出称为外延(epi.)沟道晶体管或者反转(retrograde)沟道晶体管作为理想器件结构，其在抑制短沟道效应的同时不会引起迁移率下降。对于这种晶体管，沟道区域的表面层保持具有极低的杂质浓度或者处于未掺杂状态，但是其下层具有高杂质浓度。在这种晶体管中，由于载流子在表面层上形成的反型层(inversion layer)中移动而抑制了因杂质散射引起的迁移率下降，同时通过表面层下方高掺杂的下层防止漏极耗尽层的延长，从而抑制短沟道效应。
[专利文献1]日本特开平No.2004-153246
然而，尽管上述晶体管结构作为器件的构造模型是理想的，但是当前还没有提出一种较佳的方式实现这种结构。特别对于外延沟道晶体管，因为杂质在激活退火或其他热处理期间会发生扩散，因而极难实现这种理想的阶梯式分布(step-profile)的杂质浓度。
发明内容
鉴于上述问题，本发明的目的是提供一种具有高可靠性的半导体器件及其制造方法，借此，能够容易且重复实现沟道区域内的理想阶梯式分布，从而同时实现抑制短沟道效应以及防止迁移率下降，此外能够适应(cope with)进一步缩短的沟道长度。
本发明的半导体器件的制造方法，包括如下步骤：将第一导电类型的第一杂质引入半导体衬底的半导体区域中，并且激活所述第一杂质；在所述半导体区域上形成半导体膜，该半导体膜具有等于或低于1×1016/cm3的杂质浓度；从所述半导体膜到所述半导体区域的预定深度进行非晶化；在非晶化的半导体膜上经栅极绝缘体将栅电极图案化；从所述栅电极两侧的所述非晶化的半导体膜将第二导电类型的第二杂质引入半导体区域中，并且形成源极区和漏极区；激活引入的所述第二杂质，并且通过进行热处理将所述非晶化的半导体膜和所述半导体区域的非晶化部分再结晶。
本发明的半导体器件，包括：半导体衬底，该半导体衬底具有在其上限定的有源区且具有引入到所述有源区中的第一导电类型的第一杂质；源极区和漏极区，其通过将第二导电类型的第二杂质引入所述有源区而形成；以及栅电极，其在所述有源区的所述源极区与所述漏极区之间的沟道区域上经栅极绝缘体被图案化，其中，所述有源区在比所述源极区和所述漏极区与所述有源区的界面深度深的部分上形成有残留缺陷面，并且从所述有源区的表面到所述残留缺陷面的区域从非晶状态被再结晶，并且所述沟道区域形成为其表面层基本上不含有杂质，从而在所述表面层与内部的界面处所述第一杂质的浓度以陡峭的阶梯方式增加。
附图说明
图1A至1E是以工序顺序来说明按照本实施例的CMOS晶体管的制造方法的横截面示意图；
图2A至2C是在图1A至1E之后、以工序顺序来说明按照本实施例的CMOS晶体管的制造方法的横截面示意图；
图3A和3B是在图2A至2C之后、以工序顺序来说明按照本实施例的CMOS晶体管的制造方法的横截面示意图；
图4A和4B是在图3A至3B之后、以工序顺序来说明按照本实施例的CMOS晶体管的制造方法的横截面示意图；
图5是描述按照本实施例的CMOS晶体管的沟道区域中的杂质浓度分布的横截面示意图；以及
图6是说明按照本实施例的CMOS晶体管的沟道区域中的杂质浓度分布的特性图。
具体实施方式
本发明的基本要点
本发明人进行了各种努力以容易且可靠地实现沟道区域中的理想阶梯式分布，并提出如下所述的本发明。
首先，为了确保基本完全的阶梯式分布条件作为初始状态，将杂质引入衬底的半导体区域中，形成沟道扩散层，随后通过选择性外延生长等在沟道扩散层上形成将作为沟道区域表面层的无杂质半导体膜，用以作为沟道区域的表面层。
假定上述初始状态，则需要保持相对较低的处理温度来防止杂质扩散，以便在制造过程中保持初始状态的基本完全的阶梯式分布。在处理中，激活引入源极区和漏极区(以及延伸区)中的杂质的热处理通常需要950℃至1050℃范围内的高温。本发明人特别注意这一点，提出使用称为低温固相外延再生长、在低温下进行杂质激活处理的方法。
在这种情况下，从半导体膜起将半导体区域非晶化到预定深度，并在这种状态下引入杂质以使其成为源极区和漏极区(以及延伸区)。从防止杂质也从形成深结(deep junction)的源极区和漏极区扩散以及实现高激活率的观点来看，要求该预定深度比源极区和漏极区与半导体区域的结平面深。然后，例如通过低温固相外延再生长，激活杂质并且使非晶部分再结晶。低温固相外延再生长所需的处理温度在450℃至650℃的范围内，这能抑制杂质热扩散到半导体膜中。由此，能实现高杂质激活率，并且能保持初始陡峭的阶梯式分布，而没有杂质扩散到半导体表面层中。以这种方式，可实现具有较高的短沟道容限和优良的驱动性能的半导体器件。
这里，在栅极绝缘体形成处理和栅电极形成处理中，处理温度也保持在650℃或650℃以下，以便在整个制造过程中保持较低的处理温度并且可靠地保持初始阶梯式分布。作为具体的方式，例如可使用高介电常数材料通过CVD方法来形成栅极绝缘体，并使用金属材料通过溅射或CVD方法来形成栅电极。特别是当通过普通的热氧化来形成栅极绝缘体时，需要具备超过800℃的高温作为处理温度。反之，当使用高介电常数材料通过CVD来形成栅极绝缘体时，处理温度可等于或低于650℃。类似地，当使用金属材料通过溅射来形成栅电极时，处理温度也可等于或低于650℃。
这里，在专利文献1中公开了在形成沟道扩散层之后使半导体衬底非晶化的技术。然而在这种情况下，通过将作为P型杂质的In离子注入到衬底表面层，形成P型沟道扩散层作为沟道扩散层。然后，从防止因注入较重的In离子而形成位错环缺陷层、从而在P型沟道扩散层与衬底之间的界面处产生漏电流的观点来看，通过在形成P型沟道扩散层之后将衬底内的较深部分非晶化，可以认为在衬底中将位错环缺陷层向下压低。
另一方面，本发明是通过基本上处于未掺杂状态的半导体膜来替换沟道扩散层从而可靠地实现上述阶梯式分布的技术。由此，本发明与专利文献1的发明明显不同。
此外，尽管已经开发出仅使与源极区和漏极区局部交叠的延伸区非晶化并且通过低温固相外延再生长来激活杂质的技术，但是与对比文件1中的问题一样，由于留在延伸区边缘的沟道内的位错环缺陷层而可能产生漏电流。
应用本发明的具体实施例
下面，将基于上述基本原理，参照附图详细描述将本发明应用于CMOS晶体管的具体实施例。为了举例说明，将与CMOS晶体管的制造方法一起描述具有CMOS晶体管构造的实施例。
图1A至4B是以工序顺序说明按照本实施例的CMOS晶体管的制造方法的横截面示意图。
首先，如图1A所示，在硅衬底1上限定P型MOS晶体管的有源区2和N型MOS晶体管的有源区3。
具体地，在半导体衬底(这里是硅衬底1)上的P型MOS晶体管的元件隔离区域和N型MOS晶体管的元件隔离区域中形成元件隔离结构，以限定有源区2和3。作为元件隔离结构，通过STI(浅沟槽隔离)方法形成STI元件隔离结构4，其中通过光刻和干蚀刻在元件隔离区域上形成沟槽4a，并且以比如二氧化硅等绝缘体来填充沟槽4a。这里，代替形成STI元件隔离结构4，例如可通过按照LOCOS方法场氧化元件隔离区域来形成场氧化膜。
随后，如图1B所示，在P型MOS晶体管的有源区2上形成N型阱5和N型下沟道层6，并且在NMOS晶体管的有源区3上形成P型阱7和P型下沟道层8。
具体地，通过热氧化在有源区2和3的表面上首先形成牺牲氧化物膜10。
接下来，形成仅覆盖有源区3的抗蚀掩模(未示出)，并且在下面的条件下：例如加速能量为400keV且剂量为2×1013/cm2，以及加速能量为150keV且剂量为3×1012/cm2，将N型杂质(在这种情况下为磷(P))离子注入到有源区2中以形成N型阱。在离子注入中可使用砷(As)来代替P。
接着，仍然利用覆盖有源区3的抗蚀掩模，在下面的条件下：例如加速能量为80keV且剂量是3×1012/cm2，将N型杂质(在这种情况下为砷(As))离子注入到有源区2的表面层以形成N型沟道层。在离子注入中可使用磷(P)代替As。
接下来，在通过灰化等去除覆盖有源区3的抗蚀掩模之后，形成仅覆盖有源区2的抗蚀掩模(未示出)。然后，利用该抗蚀掩模，在下面的条件下：例如加速能量为180keV且剂量为2×1013/cm2，以及加速能量为50keV且剂量为4×1012/cm2，将P型杂质(在这种情况下为硼(B))离子注入到有源区3以形成P型阱。
接着，仍然利用覆盖有源区2的抗蚀掩模，在下面的条件下：例如加速能量为8keV且剂量为5×1012/cm2，将P型杂质(在这种情况下为硼(B))离子注入到有源区3的表面层以形成P型沟道层。这里，在离子注入中可使用铟(In)代替B。
通过灰化等去除覆盖有源区2的抗蚀掩模，之后在1000℃的处理温度下进行约10秒的热处理(退火)。该退火激活离子注入的杂质，修复由离子注入引起的缺陷，在有源区2中形成N型阱5和N型下沟道层6，并且在有源区3中形成P型阱7和P型下沟道层8。此外，形成P型和N型MOS晶体管的有源区(杂质注入)的顺序可以颠倒。
随后，如图1C所示，在下沟道层6和8上形成未掺杂状态(杂质浓度等于或低于1×1016/cm3)的上沟道层9。
具体地，通过湿蚀刻等首先去除有源区2和3的牺牲氧化物膜10。
然后，通过选择性外延生长，在下沟道层6和8上生长处于未掺杂状态、膜厚约为10nm的半导体膜，在这种情况下为硅膜，以形成上沟道层9。
随后，如图1D所示，从上沟道层9到包含下沟道层6和8的预定深度将半导体衬底1非晶化。
具体地，使用相对较重的元素，在这种情况下为Ge，从上沟道层9注入到衬底，以从上沟道层9到包含下沟道层6和8的预定深度(由虚线D所示)将半导体衬底1非晶化。这里，预定深度D需要比如下所述的源极区域17、22和漏极区域18、23与半导体衬底1的结平面深。此外，在注入中可使用Si或Ar代替Ge。
接下来，如图1E所示，在P型MOS晶体管的有源区2中于上沟道层9上经栅极绝缘体11形成栅电极12和覆盖绝缘体(cap insulator)20，而在N沟道MOS晶体管的有源区3中于上沟道层9上经栅极绝缘体13形成栅电极14和覆盖绝缘体20。
具体地，在有源区2和3中，利用高介电常数材料，在这种情况下为HfSiON，于上沟道层9上形成栅极绝缘体11和13。这里，在等于或低于650℃的处理温度下，例如450℃，通过CVD形成栅极绝缘体11。在这种情况下，由于处理温度相对较低，即等于或低于650℃，因此能够防止下沟道层6和8中的杂质扩散到上沟道层9。此外，作为栅极绝缘体11的材料，可使用HfSiO2、ZrO2等代替HfSiON。
接着，在使用金属材料(在这种情况下为W/TiN)于栅极绝缘体11和13上沉积金属膜(未示出)之后，在有源区2和3中沉积例如二氧化硅膜作为覆盖材料。例如通过溅射在处理温度等于或低于650℃，例如为100℃时形成金属膜。在这种情况下，由于处理温度相对较低，即等于或低于650℃，因此能够防止下沟道层6和8中的杂质扩散到上沟道层9。
然后，形成抗蚀掩模(未示出)以仅露出有源区2和3的栅电极形成区域。利用这层抗蚀掩模，分别将有源区2和3的二氧化硅膜、金属膜和栅极绝缘体11和13图案化。通过进行图案化，在有源区2中经栅极绝缘体11将栅电极12和覆盖绝缘体20图案化，并在有源区3中经栅极绝缘体13将电极14和覆盖绝缘体20图案化栅。
接下来，如图2A所示，在P型MOS晶体管的有源区2上形成P型延伸区15。
具体地，形成仅覆盖有源区3的抗蚀掩模31，并且在下面的条件下：例如加速能量为0.5keV且剂量为1×1015/cm2，将P型杂质(在这种情况下为硼(B))离子注入到有源区2中。在这种情况下，利用覆盖绝缘体20和栅电极12作为掩模，在栅电极12两侧的有源区2中形成P型延伸区15。此外，由于将被离子注入的区域已被非晶化，所以能够防止由于沟道效应(channeling)而引起结深增加。
接着，如图2B所示，在N型MOS晶体管的有源区3上形成N型延伸区19。
具体地，在通过灰化等去除覆盖有源区3的抗蚀掩模31之后，形成仅覆盖有源区2的抗蚀掩模32。然后，利用抗蚀掩模32，在下面的条件下：例如加速能量为5keV且剂量为1.5×1015/cm2，将N型杂质(在这种情况下为砷(As))离子注入到有源区3中。在这种情况下，利用覆盖绝缘体20和栅电极14作为掩模，在栅电极14两侧的有源区3中形成N型延伸区19。此外，由于将被离子注入的区域已被非晶化，所以能够防止由于隧穿而引起结深增大。
随后，如图2C所示，同时形成侧壁间隔物16和21：前者形成在P型MOS晶体管的有源区2中覆盖绝缘体20和栅电极12的两侧上，后者形成在N型MOS晶体管的有源区3中覆盖绝缘体20和栅电极14的两侧上。
具体地，在通过灰化等去除覆盖有源区2的抗蚀掩模32之后，沉积一层绝缘体，在这种情况下为二氧化硅膜(未示出)，以便覆盖栅电极12和14的整个表面。然后在二氧化硅膜的整个表面上进行各向异性蚀刻(回蚀刻)以形成侧壁间隔物16和21，仅在有源区2中的覆盖绝缘体20和栅电极12的两侧上、以及仅在有源区3中的覆盖绝缘体20和栅电极14的两侧上留下二氧化硅膜。
随后，如图3A所示，在P型MOS晶体管的有源区2上形成P型源极区17和漏极区18。
具体地，形成仅覆盖有源区3的抗蚀掩模33，并且在下面的条件下：例如加速能量为5keV且剂量为4×1015/cm2，将P型杂质(在这种情况下为硼(B))离子注入到有源区2。在这种情况下，利用覆盖绝缘体20、栅电极12和侧壁间隔物16作为掩模，形成比P型延伸区15深的P型源极区17和漏极区18，以使其在侧壁间隔物16两侧的有源区2中与延伸区15部分交叠。这里，由于非晶化部分的预定深度D比源极区17、漏极区18与硅衬底1的结平面深，所以在非晶化部分上形成延伸区15、源极区17和漏极区18。
随后，如图3B所示，在N型MOS晶体管的有源区3上形成N型源极区22和漏极区23。
具体地，在通过灰化等去除覆盖有源区3的抗蚀掩模33之后，形成仅覆盖有源区2的抗蚀掩模34，并且在下面的条件下：例如加速能量为20keV且剂量为5×1015/cm2，将N型杂质(在这种情况下为磷(P))离子注入到有源区3中。在这种情况下，利用覆盖绝缘体20、栅电极14和侧壁间隔物21作为掩模，形成比N型延伸区19深的N型源极区22和漏极区23，以使其在侧壁间隔物21两侧的有源区3中与延伸区19部分交叠。这里，由于非晶化部分的预定深度D比源极区22、漏极区23与硅衬底1的结平面深，所以在非晶化部分上形成延伸区19、源极区22和漏极区23。
随后，如图4A所示，通过低温固相外延再生长激活在上述非晶化之后引入的各种杂质，并且使非晶化部分再结晶。
具体地，通过灰化首先去除覆盖有源区2的抗蚀掩模34。
然后，在450℃至650℃范围内的处理温度(在这种情况下为600℃)下，通过30分钟的低温固相外延再生长激活在上述非晶化之后引入的各种杂质激活，这些杂质是有源区2中延伸区15、源极区17和漏极区18的受主，以及有源区3中延伸区19、源极区22和漏极区23的施主；同时将非晶化部分，即硅衬底1中处于预定深度D或者之上的部分(包含下沟道层6和8)以及上沟道层9再结晶。这里，在预定深度D的位置，作为非晶化部分再结晶时的记录(history)，在预定深度D的位置留下残留的缺陷面(由虚线R所示)。
这里，在允许整个非晶部分结晶化的范围内，低温固相外延再生长的持续时间优选为尽可能短。
在这种情况下，由于处理温度相对较低，即等于或低于650℃，所以能够防止下沟道层6和8中的杂质扩散到上沟道层9。此外，由于低温处理，在延伸区15和19、源极区17和22以及漏极区18和23中的各种杂质被充分激活，而不会扩散到各个上沟道层9中。请注意，尽管这里描述的延伸区、源极/漏极区的形成顺序(离子注入的顺序)为例如P型MOSFET在先，N型MOSFET在后，但是该顺序可以颠倒。此外，在注入延伸区杂质之后，可注入袋区杂质(pocket impurity)作为击穿停止层(punch-through stopper).
随后，如图4B所示，在源极区17及22和漏极区18及23上形成硅化物层24。
具体地，通过溅射等将金属例如Co或Ni沉积在包含有源区2和3的整个表面上，并且通过在650℃或650℃以下的较低处理温度(在这种情况下为400℃)下进行30秒的热处理、并使沉积的金属与源极区17和22以及漏极区18和23上的硅发生反应，形成硅化物层24。然后通过湿蚀刻去除未与硅反应的金属。此外，在低于650℃的低温(在这种情况下为500℃)下进行30秒的热处理以制成完全的硅化物。在这次湿蚀刻处理期间，由于在栅电极12和14上存在覆盖绝缘体20，因此保护了栅电极12和14免受蚀刻。
随后，在形成层间绝缘体、各种连接孔和布线之后，制成CMOS晶体管，其在有源区2中具有P型MOS晶体管，并在有源区3中具有N型MOS晶体管。
在本实施例中，在整个制造工艺期间保持较低的处理温度，即650℃或650℃以下，以通过低温固相外延再生长来激活杂质并使非晶化部分再结晶，由此抑制了杂质热扩散到各个上沟道层9，从而在防止杂质扩散到各个上沟道层9的同时产生较高的杂质激活率。因此，在这样的条件下，即在硅膜形成各个上沟道层9之后立即在沟道区域即有源区2的上沟道层9和下沟导层6中、以及在有源区3的上沟道层9和下沟道层8中保持初始陡峭的阶梯式分布，而制成CMOS晶体管。
作为实例，检验有源区2中P型MOS晶体管的沟道区域中的浓度分布。这里，如图5中所示的虚线L，沿着P型MOS晶体管的沟道区域的深度方向检验浓度分布(对应于图4B)。结果，尽管上沟道层9的杂质浓度极低且基本上未掺杂(不含有杂质的状态)，但是下沟道层6的杂质浓度显示出相当高的值，且阱5的杂质浓度从下沟道层6的杂质浓度开始逐渐降低。这里，能够看出获得了所谓的阶梯式分布，其中杂质浓度在上沟道层9与下沟道层6之间的界面处急剧改变。
利用本实施例的CMOS晶体管，由于载流子穿过基本上未掺杂的各个上沟道层9迁移，因此抑制了迁移率的下降；并且通过具有较高杂质浓度的下沟道层6和8抑制了短沟道效应。因此，如所述，按照本实施例能够容易且可靠地实现沟道区域中的理想阶梯式分布，并且能同时抑制短沟道效应及防止迁移率下降，由此能获得可适应短沟道长度且具有高可靠性的CMOS晶体管。
按照本发明，能够容易且重复地实现源极/漏极杂质的高水平激活率以及沟道区域中的理想阶梯式分布，由此能同时抑制短沟道效应及防止迁移率下降，从而能够制造出可适应进一步缩短的沟道长度且具有高可靠性的半导体器件。

Claims (13)

1.一种半导体器件的制造方法，包括如下步骤：
将第一导电类型的第一杂质引入半导体衬底的半导体区域中，并且激活所述第一杂质；
在所述半导体区域上形成半导体膜，该半导体膜具有等于或低于1×1016/cm3的杂质浓度；
从所述半导体膜到所述半导体区域的预定深度进行非晶化；
在非晶化的半导体膜上经栅极绝缘体将栅电极图案化；
从所述栅电极两侧的所述非晶化的半导体膜将第二导电类型的第二杂质引入半导体区域中，并且形成源极区和漏极区；
激活引入的所述第二杂质，并且通过进行热处理将所述非晶化的半导体膜和所述半导体区域的非晶化部分再结晶。
2.如权利要求1所述的半导体器件的制造方法，其特征在于所述非晶化步骤中所述半导体区域非晶化达到的深度比所述源极区和所述漏极区与所述半导体区域的界面深度深。
3.如权利要求1所述的半导体器件的制造方法，其特征在于在450℃至650℃范围内的温度下进行所述热处理。
4.如权利要求1所述的半导体器件的制造方法，其特征在于在等于或低于650℃的温度下形成所述栅极绝缘体。
5.如权利要求4所述的半导体器件的制造方法，其特征在于由HfSiON、HfsiO2和ZrO2三种材料之一形成所述栅极绝缘体。
6.如权利要求1所述的半导体器件的制造方法，其特征在于在等于或低于650℃的温度下形成所述栅电极。
7.如权利要求6所述的半导体器件的制造方法，其特征在于由金属材料形成所述栅电极。
8.如权利要求1所述的半导体器件的制造方法，其特征在于通过选择性外延生长形成所述半导体膜。
9.一种半导体器件，包括：
半导体衬底，该半导体衬底具有在其上限定的有源区和引入到所述有源区中的第一导电类型的第一杂质；
源极区和漏极区，其通过将第二导电类型的第二杂质引入所述有源区而形成；以及
栅电极，其在所述有源区的所述源极区与所述漏极区之间的沟道区域上经栅极绝缘体被图案化，其中，
所述有源区在比所述源极区和所述漏极区与所述有源区的界面深度深的部分上形成有残留缺陷面，并且从所述有源区的表面到所述残留缺陷面的区域从非晶状态被再结晶，并且
所述沟道区域形成为其表面层基本上不含有杂质，从而在所述表面层与所述沟道区域内部的界面处所述第一杂质的浓度以陡峭的阶梯方式增加。
10.如权利要求9所述的半导体器件，其特征在于所述沟道区域的所述表面层由在所述有源区中形成的半导体膜构成。
11.如权利要求10所述的半导体器件，其特征在于通过选择性外延生长形成所述半导体膜。
12.如权利要求9所述的半导体器件，其特征在于，由HfSiON、HfSiO2和ZrO2三种材料之一形成所述栅极绝缘体。
13.如权利要求9所述的半导体器件，其特征在于，由金属材料形成所述栅电极。
CNB2005100994963A 2005-03-30 2005-09-06 半导体器件及其制造方法 Expired - Fee Related CN100495662C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005099802 2005-03-30
JP2005099802A JP4493536B2 (ja) 2005-03-30 2005-03-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN1841680A CN1841680A (zh) 2006-10-04
CN100495662C true CN100495662C (zh) 2009-06-03

Family

ID=37030616

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100994963A Expired - Fee Related CN100495662C (zh) 2005-03-30 2005-09-06 半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US7223646B2 (zh)
JP (1) JP4493536B2 (zh)
KR (1) KR100713680B1 (zh)
CN (1) CN100495662C (zh)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100771552B1 (ko) * 2006-10-31 2007-10-31 주식회사 하이닉스반도체 숏 채널 효과가 억제되는 모스트랜지스터 및 그 제조방법
KR100934789B1 (ko) * 2007-08-29 2009-12-31 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
EP2113940A1 (en) * 2008-04-30 2009-11-04 Imec A method for producing NMOS and PMOS devices in CMOS processing
JP2010135644A (ja) * 2008-12-05 2010-06-17 Advanced Lcd Technologies Development Center Co Ltd 薄膜半導体装置及びその製造方法
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
KR101669470B1 (ko) 2009-10-14 2016-10-26 삼성전자주식회사 금속 실리사이드층을 포함하는 반도체 소자
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
JP5621381B2 (ja) 2010-07-28 2014-11-12 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5630185B2 (ja) * 2010-09-30 2014-11-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5578001B2 (ja) * 2010-09-30 2014-08-27 富士通セミコンダクター株式会社 半導体装置の製造方法
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
CN104269358A (zh) * 2014-09-16 2015-01-07 复旦大学 半导体器件的制备方法
TWI550716B (zh) * 2015-07-08 2016-09-21 力晶科技股份有限公司 半導體元件的製造方法
US10522534B2 (en) 2016-04-29 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET varactor with low threshold voltage and method of making the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846194A (en) * 1973-01-05 1974-11-05 Inselek Inc Process for producing lightly doped p and n-type regions of silicon on an insulating substrate
JPH07321313A (ja) * 1994-05-24 1995-12-08 Sanyo Electric Co Ltd 半導体デバイスの製造方法
KR100325297B1 (ko) * 1997-12-26 2002-04-17 박종섭 반도체 소자의 제조방법
US6399458B1 (en) * 1999-09-21 2002-06-04 International Business Machines Corporation Optimized reachthrough implant for simultaneously forming an MOS capacitor
US6174754B1 (en) * 2000-03-17 2001-01-16 Taiwan Semiconductor Manufacturing Company Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors
WO2003009385A1 (fr) * 2001-07-19 2003-01-30 Sharp Kabushiki Kaisha Dispositif a semi-conducteur, dispositif de stockage a semi-conducteur et procedes de production associes
JP2003086706A (ja) * 2001-09-13 2003-03-20 Sharp Corp 半導体装置及びその製造方法、スタティック型ランダムアクセスメモリ装置並びに携帯電子機器
JP4639040B2 (ja) * 2002-10-10 2011-02-23 パナソニック株式会社 半導体装置の製造方法
JP2005101196A (ja) * 2003-09-24 2005-04-14 Hitachi Ltd 半導体集積回路装置の製造方法
US20060157732A1 (en) * 2004-11-09 2006-07-20 Epispeed Sa Fabrication of MOS-gated strained-Si and SiGe buried channel field effect transistors

Also Published As

Publication number Publication date
US7223646B2 (en) 2007-05-29
US20070205441A1 (en) 2007-09-06
JP2006278974A (ja) 2006-10-12
US20060220114A1 (en) 2006-10-05
CN1841680A (zh) 2006-10-04
JP4493536B2 (ja) 2010-06-30
KR100713680B1 (ko) 2007-05-02
KR20060106567A (ko) 2006-10-12
US7312500B2 (en) 2007-12-25

Similar Documents

Publication Publication Date Title
CN100495662C (zh) 半导体器件及其制造方法
CN100470737C (zh) 半导体元件的制造方法
US6165825A (en) Semiconductor device and method for producing the same
JPH11168069A (ja) 半導体装置の製造方法
KR100315900B1 (ko) 반도체 장치의 제조 방법
US6734109B2 (en) Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon
CN102655150A (zh) 半导体器件以及半导体器件的制造方法
US8877619B1 (en) Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9112020B2 (en) Transistor device
US6709961B2 (en) Method for fabricating semiconductor device
US6417038B1 (en) Method of fabricating semiconductor device
CN101933133A (zh) 制造双取向iv族半导体衬底的方法
CN101150072A (zh) 半导体器件
KR100607317B1 (ko) 반도체소자의접합부형성방법
KR100406588B1 (ko) 반도체 소자의 제조방법
KR100477940B1 (ko) 반도체 소자의 얇은 접합 형성 방법
KR100679812B1 (ko) 모스 트랜지스터 및 그 제조 방법
JPH09162396A (ja) 半導体装置の製造方法
KR101128699B1 (ko) 반도체 소자의 제조방법
JP2608627B2 (ja) 半導体装置の製造方法
KR20040001792A (ko) 반도체 소자의 제조 방법
JPH0415950A (ja) 相補型電界効果半導体装置およびその製造方法
KR970072206A (ko) 반도체 소자의 트랜지스터 제조 방법
JPH04206950A (ja) 半導体装置の製造方法
US20080054315A1 (en) Method for manufacturing semiconductor device by using two step pocket implant process

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081107

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20081107

Address after: Tokyo, Japan

Applicant after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kanagawa

Applicant before: Fujitsu Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Japan's Kanagawa Prefecture Yokohama

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090603

Termination date: 20190906

CF01 Termination of patent right due to non-payment of annual fee