JP5578001B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5578001B2 JP5578001B2 JP2010220775A JP2010220775A JP5578001B2 JP 5578001 B2 JP5578001 B2 JP 5578001B2 JP 2010220775 A JP2010220775 A JP 2010220775A JP 2010220775 A JP2010220775 A JP 2010220775A JP 5578001 B2 JP5578001 B2 JP 5578001B2
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- 229910052787 antimony Inorganic materials 0.000 description 1
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Description
一実施形態による半導体装置及びその製造方法について図1乃至図20を用いて説明する。
参考例による半導体装置の製造方法について図21乃至図26を用いて説明する。図1乃至図20に示す一実施形態による半導体装置及びその製造方法と同様の構成要素には同一の符号を付し説明を省略し或いは簡潔にする。
上記実施形態に限らず種々の変形が可能である。
12…溝
14,52,60,64…シリコン酸化膜
16…低電圧NMOSトランジスタ形成領域
18,26,34,42,50,62…フォトレジスト膜
20,36…Pウェル
22…P型高濃度不純物層
24…低電圧PMOSトランジスタ形成領域
28,44…Nウェル
30…N型高濃度不純物層
32…高電圧NMOSトランジスタ形成領域
38,70,74…P型不純物層
40…高電圧PMOSトランジスタ形成領域
46,68,72…N型不純物層
48…シリコン層
54…シリコン窒化膜
56…素子分離溝
58…素子分離絶縁膜
60a,64a…ゲート絶縁膜
66a…ポリシリコン膜
66…ゲート電極
76…サイドウォールスペーサ
78…N型不純物層(ソース/ドレイン領域)
80…P型不純物層(ソース/ドレイン領域)
84…金属シリサイド膜
86…層間絶縁膜
88…コンタクトプラグ
90…配線
92…アモルファス層
94…結晶欠陥
100…シリコン基板
102…ソース領域
104…ドレイン領域
106…チャネル領域
108…高濃度不純物層
110…シリコン層
112…ゲート絶縁膜
114…ゲート電極
Claims (8)
- 半導体基板にイオン注入を行い、前記半導体基板の第1の領域及び第2の領域を非晶質化する工程の後に、
前記半導体基板の前記第1の領域に、第1導電型の第1の不純物をイオン注入する工程と、
前記半導体基板の前記第2の領域に、第2導電型の第2の不純物をイオン注入する工程と、
前記第1の不純物及び前記第2の不純物を活性化し、前記第1の領域に第1の不純物層を、前記第2の領域に第2の不純物層を、それぞれ形成する工程と、
前記第1の不純物層及び前記第2の不純物層が形成された前記半導体基板上に、半導体層をエピタキシャル成長する工程と、
前記半導体層の前記第1の領域上及び前記第2の領域上に、ゲート絶縁膜を成長する工程と、
前記第1の領域の前記ゲート絶縁膜上に第1のゲート電極を、前記第2の領域の前記第ゲート絶縁膜上に第2のゲート電極を、それぞれ形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 半導体基板にイオン注入を行い、前記半導体基板の第1の領域、第2の領域、第3の領域、及び第4の領域を非晶質化する工程の後に、
前記半導体基板の前記第1の領域に、第1導電型の第1の不純物をイオン注入する工程と、
前記半導体基板の前記第2の領域に、第2導電型の第2の不純物をイオン注入する工程と、
前記半導体基板の前記第3の領域に、前記第1導電型の第3の不純物をイオン注入する工程と、
前記半導体基板の前記第4の領域に、前記第2導電型の第4の不純物をイオン注入する工程と、
前記第1の不純物、前記第2の不純物、前記第3の不純物、及び前記第4の不純物を活性化し、前記第1の領域に第1の不純物層を、前記第2の領域に第2の不純物層を、前記第3の領域に第3の不純物層を、前記第4の領域に第4の不純物層を、それぞれ形成する工程と、
前記第1の不純物層、前記第2の不純物層、前記第3の不純物層、及び前記第4の不純物層が形成された前記半導体基板上に、半導体層をエピタキシャル成長する工程と、
前記半導体層の前記第1の領域、前記第2の領域、前記第3の領域、及び前記第4の領域上に、第1のゲート絶縁膜を成長する工程と、
前記第1の領域及び前記第2の領域の前記第1のゲート絶縁膜を除去する工程と、
前記半導体層の前記第1の領域及び前記第2の領域上に、前記第1のゲート絶縁膜よりも薄い第2のゲート絶縁膜を成長する工程と、
前記第1の領域の前記第2のゲート絶縁膜上に第1のゲート電極を、前記第2の領域の前記第2のゲート絶縁膜上に第2のゲート電極を、前記第3の領域の前記第1のゲート絶縁膜上に第3のゲート電極を、前記第4の領域の前記第1のゲート絶縁膜上に第4のゲート電極を、それぞれ形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項1又は2に記載の半導体装置の製造方法において、
前記半導体基板を非晶質化する工程では、マスクを用いずに、前記半導体基板にイオン注入を行う
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至3のいずれか1項に記載の半導体装置の製造方法において、
前記半導体基板を非晶質化する工程では、前記半導体基板にゲルマニウム又はシリコンをイオン注入する
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至4のいずれか1項に記載の半導体装置の製造方法において、
前記第1のゲート電極及び前記第2のゲート電極を形成する工程の後、前記第1の領域の前記半導体層及び前記半導体基板に前記第2導電型の第1のソース/ドレイン領域を形成する工程と、前記第2の領域の前記半導体層及び前記半導体基板に前記第1導電型の第2のソース/ドレイン領域を形成する工程とを更に有し、
前記半導体基板を非晶質化する工程では、前記半導体基板に形成される非晶質層の深さが前記第1のソース/ドレイン領域及び前記第2のソース/ドレイン領域よりも深くなるように、前記半導体基板を非晶質化する
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至5のいずれか1項に記載の半導体装置の製造方法において、
前記第1の不純物は、ボロン及び炭素を含む
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至6のいずれか1項に記載の半導体装置の製造方法において、
前記第2の不純物は、砒素を含む
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至7のいずれか1項に記載の半導体装置の製造方法において、
前記半導体層を形成する工程の後、前記半導体層を形成した前記半導体基板に素子分離絶縁膜を形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。
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JP5837387B2 (ja) * | 2011-10-11 | 2015-12-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置および半導体集積回路装置の製造方法 |
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