CN100482041C - 印刷布线板 - Google Patents
印刷布线板 Download PDFInfo
- Publication number
- CN100482041C CN100482041C CN03811141.1A CN03811141A CN100482041C CN 100482041 C CN100482041 C CN 100482041C CN 03811141 A CN03811141 A CN 03811141A CN 100482041 C CN100482041 C CN 100482041C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- pad
- conductive pattern
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000615 nonconductor Substances 0.000 claims description 8
- 238000005452 bending Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 239000012774 insulation material Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 description 21
- 239000011810 insulating material Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002143530 | 2002-05-17 | ||
JP143530/2002 | 2002-05-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1653871A CN1653871A (zh) | 2005-08-10 |
CN100482041C true CN100482041C (zh) | 2009-04-22 |
Family
ID=29545023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN03811141.1A Expired - Fee Related CN100482041C (zh) | 2002-05-17 | 2003-05-19 | 印刷布线板 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7180005B2 (zh) |
JP (1) | JP4341552B2 (zh) |
CN (1) | CN100482041C (zh) |
TW (1) | TW591981B (zh) |
WO (1) | WO2003098983A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105979716A (zh) * | 2016-05-20 | 2016-09-28 | 泉州三宝电子有限公司 | 一种柔性电路板及其制造方法 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE47600E1 (en) * | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
JP4618260B2 (ja) * | 2007-02-21 | 2011-01-26 | 日本テキサス・インスツルメンツ株式会社 | 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置 |
JP5331371B2 (ja) | 2007-04-24 | 2013-10-30 | パナソニック株式会社 | 電子部品パッケージ、回路基板、電子部品実装装置、およびそれらの接合部の検査方法 |
JP2009105139A (ja) * | 2007-10-22 | 2009-05-14 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法と半導体装置 |
FR2924302B1 (fr) * | 2007-11-23 | 2010-10-22 | St Microelectronics Grenoble | Procede de fabrication de plots de connexion electrique d'une plaque |
JP5053919B2 (ja) * | 2008-03-07 | 2012-10-24 | パナソニック株式会社 | 表面実装デバイスの実装構造体 |
US8138616B2 (en) * | 2008-07-07 | 2012-03-20 | Mediatek Inc. | Bond pad structure |
JP2014049608A (ja) * | 2012-08-31 | 2014-03-17 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
JP2014072371A (ja) * | 2012-09-28 | 2014-04-21 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
JP2014072370A (ja) * | 2012-09-28 | 2014-04-21 | Ibiden Co Ltd | プリント配線板及びプリント配線板の製造方法 |
CN104105340A (zh) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | 一种封装基板导通孔结构及制作方法 |
KR102419900B1 (ko) * | 2015-09-02 | 2022-07-13 | 삼성전자주식회사 | 인쇄회로기판 장치 및 이를 포함하는 전자 장치 |
JP2017103367A (ja) * | 2015-12-02 | 2017-06-08 | ローム株式会社 | 実装基板およびその製造方法、ならびに、実装基板および電子部品を備えた実装構造 |
JP6750872B2 (ja) | 2016-09-01 | 2020-09-02 | キヤノン株式会社 | プリント配線板、プリント回路板及び電子機器 |
US10658292B2 (en) * | 2017-04-24 | 2020-05-19 | Taiwan Semiconductor Manufacturing Company Limited | Metal patterning for internal cell routing |
JP2021501710A (ja) | 2017-10-01 | 2021-01-21 | スペース ファウンドリー インコーポレイテッド | プラズマジェット印刷用のモジュール式プリントヘッドアセンブリ |
CN108235568A (zh) * | 2018-01-19 | 2018-06-29 | 华南理工大学 | 一种将pth通孔去除内层非功能pad的pcb板 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4064357A (en) * | 1975-12-02 | 1977-12-20 | Teledyne Electro-Mechanisms | Interconnected printed circuits and method of connecting them |
JPS5849637Y2 (ja) * | 1978-07-14 | 1983-11-12 | 株式会社日立製作所 | 厚膜配線板 |
JPS6453493A (en) * | 1987-08-24 | 1989-03-01 | Ibiden Co Ltd | Wiring board for surface packaging |
JPS6453493U (zh) | 1987-09-30 | 1989-04-03 | ||
US4859808A (en) * | 1988-06-28 | 1989-08-22 | Delco Electronics Corporation | Electrical conductor having unique solder dam configuration |
JPH04101496A (ja) * | 1990-08-20 | 1992-04-02 | Nec Corp | 印刷配線板 |
JPH04263491A (ja) * | 1991-02-19 | 1992-09-18 | Fujitsu Ltd | プリント基板 |
JPH04354398A (ja) * | 1991-05-31 | 1992-12-08 | Internatl Business Mach Corp <Ibm> | 配線基板及びその製造方法 |
US5523920A (en) * | 1994-01-03 | 1996-06-04 | Motorola, Inc. | Printed circuit board comprising elevated bond pads |
JPH08340170A (ja) * | 1995-06-12 | 1996-12-24 | Ibiden Co Ltd | プリント配線板 |
US6774474B1 (en) * | 1999-11-10 | 2004-08-10 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
-
2003
- 2003-05-19 TW TW092113445A patent/TW591981B/zh not_active IP Right Cessation
- 2003-05-19 JP JP2004506327A patent/JP4341552B2/ja not_active Expired - Fee Related
- 2003-05-19 CN CN03811141.1A patent/CN100482041C/zh not_active Expired - Fee Related
- 2003-05-19 US US10/514,657 patent/US7180005B2/en not_active Expired - Fee Related
- 2003-05-19 WO PCT/JP2003/006192 patent/WO2003098983A1/ja active Application Filing
-
2007
- 2007-01-09 US US11/621,273 patent/US20080190654A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105979716A (zh) * | 2016-05-20 | 2016-09-28 | 泉州三宝电子有限公司 | 一种柔性电路板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1653871A (zh) | 2005-08-10 |
TW591981B (en) | 2004-06-11 |
JPWO2003098983A1 (ja) | 2005-09-22 |
US20050167154A1 (en) | 2005-08-04 |
WO2003098983A1 (fr) | 2003-11-27 |
TW200308188A (en) | 2003-12-16 |
US20080190654A1 (en) | 2008-08-14 |
JP4341552B2 (ja) | 2009-10-07 |
US7180005B2 (en) | 2007-02-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100482041C (zh) | 印刷布线板 | |
US5847936A (en) | Optimized routing scheme for an integrated circuit/printed circuit board | |
US6545876B1 (en) | Technique for reducing the number of layers in a multilayer circuit board | |
US8367942B2 (en) | Low profile electrical interposer of woven structure and method of making same | |
US3670208A (en) | Microelectronic package, buss strip and printed circuit base assembly | |
JP3111053B2 (ja) | 一次スルー・ホールおよび二次スルー・ホールを有する多層回路板 | |
US4652974A (en) | Method and structure for effecting engineering changes in a multiple device module package | |
JP5254899B2 (ja) | 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト | |
US7256354B2 (en) | Technique for reducing the number of layers in a multilayer circuit board | |
KR100768291B1 (ko) | 반도체 장치의 시험 장치 및 반도체 장치의 시험 방법 | |
CN107180810A (zh) | 具有增大的附接角度的导电线的半导体装置和方法 | |
JPS62274692A (ja) | プリント回路板 | |
CN1568543B (zh) | 半导体元件 | |
CN108575044A (zh) | 印刷电路板及其组件 | |
EP1714530B1 (en) | Method for increasing a routing density for a circuit board and such a circuit board | |
CN1327519C (zh) | 器件封装件和印刷电路板及电子装置 | |
KR900005725B1 (ko) | 핀보드 매트릭스 | |
US20010040297A1 (en) | Multiple line grid for use in a packaging of a testing application | |
US8735735B2 (en) | Electronic module with embedded jumper conductor | |
CN114423176B (zh) | 包括侧面pin脚的pcb板及其制造方法、通信模组 | |
CN112214130B (zh) | 触控显示屏及显示设备 | |
CN107801295A (zh) | 柔性电路板及移动终端 | |
CN219678793U (zh) | 印刷电路板及其布线结构 | |
CN101594738B (zh) | 信号导通元件 | |
JPH05102621A (ja) | 導電パターン |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: LENOVO INNOVATION CO., LTD. (HONGKONG) Free format text: FORMER OWNER: NEC CORP. Effective date: 20141126 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; TO: HONG KONG, CHINA |
|
TR01 | Transfer of patent right |
Effective date of registration: 20141126 Address after: Hongkong, China Patentee after: LENOVO INNOVATIONS Co.,Ltd.(HONG KONG) Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090422 Termination date: 20170519 |