CN100448023C - 具有u字型栅极结构的半导体器件 - Google Patents

具有u字型栅极结构的半导体器件 Download PDF

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CN100448023C
CN100448023C CNB2003801019541A CN200380101954A CN100448023C CN 100448023 C CN100448023 C CN 100448023C CN B2003801019541 A CNB2003801019541 A CN B2003801019541A CN 200380101954 A CN200380101954 A CN 200380101954A CN 100448023 C CN100448023 C CN 100448023C
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grid
semiconductor device
insulating barrier
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CN1708855A (zh
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B·于
S·S·艾哈迈德
J·X·安
S·达克希纳-默西
Z·克里沃卡皮奇
汪海宏
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GlobalFoundries Inc
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Abstract

一种双栅极半导体器件(100)包括有衬底(110)、绝缘层(120)、鳍(210)以与栅极(510)。该绝缘层(120)形成在该衬底(110)上，而该栅极(510)形成在该绝缘层(120)上。该鳍(210)具有多个侧表面、一顶面、以及一底面。该栅极(510)围绕着鳍(210)的底面以及至少部分的侧表面。围绕该鳍(210)的栅极材料(510)在该半导体器件(100)的沟道区域具有U型剖面。

Description

具有U字型栅极结构的半导体器件
技术领域
本发明涉及半导体器件以及制造半导体器件的方法，更具体地，本发明特别适用于双栅极结构。
背景技术
超大规模集成电路半导体器件日益攀升的高密度与性能需求需要例如栅极长度小于100纳米(nm)的设计特征、高可靠度、以及更高的制造生产能力。设计特征缩减到小于100纳米是对传统方式限制的挑战。
例如，当传统的平面金属氧化物半导体场效应晶体管(MOSFET)的栅极长度缩小于100纳米时，短沟道效应的问题，例如源极与漏极间的过量的漏电，变得更难克服。并且，迁移率的降低以及其它若干工艺问题也使得调整传统MOSFET以包含更小的器件特征的困难度更大。因此需要发展新的器件结构以增进FET性能并允许更进一步的器件尺寸调整。
双栅极MOSFET视为代表超越旧有平面式MOSFET的候选者的新结构。双栅极MOSFET中，可用两个栅极控制短沟道效应。鳍式场效晶体管(FinFET)为近来双栅极结构的一种，并具有良好的短沟道性能。FinFET包括形成在垂直鳍中的沟道。可使用类似传统平面式MOSFET的版图以及工艺技术制造FinFET结构。
发明内容
按照本发明的实施方式提供具有形成在导电鳍的相对侧的两栅极的FinFET器件。该器件可包括位于导电鳍下的栅极材料，以增加器件的总沟道宽。
将在下述说明本发明的额外的优点以及其它特征将部分，而本领域技术人员透过阅读下述说明或由实施本发明也能使本发明的优点以及特征部分的更显而易见。按照权利要求书中的特别指定可获得本发明的优点以及特征。
根据本发明，可通过包括有衬底、绝缘层、第一栅极、和鳍(fin)的半导体器件来部分的获得上述以及其它好处。该绝缘层形成于该衬底上，且该第一栅极形成于该绝缘层上。该第一栅极在半导体器件的沟道区域具有U型剖面。该鳍具有多个侧表面、一顶面、以及一底面，其中该第一栅极围绕该底面以及至少一部分的侧表面。
根据本发明的另一方面，提供一种制造半导体器件的方法。该方法包括在衬底上形成绝缘层并在该绝缘层上形成鳍结构。该鳍结构具有多个侧表面、一顶面、以及一底面。该方法也包括在该鳍结构的顶面上形成电介质层，形成源极和漏极区域并蚀刻该绝缘层以横向底切位于该鳍结构底面下的绝缘层。该方法还包括在该鳍结构上沉积栅极材料，其中栅极材料围绕该鳍结构的底面以及至少一部分的侧表面。该方法也包括将沉积的栅极材料平坦化、图形化并蚀刻该栅极材料以在该鳍结构的对侧形成第一和第二栅极电极。
根据本发明的又一方面，提供一种半导体器件，包括有衬底、绝缘层、导电鳍、电介质盖、栅极电介质层、和栅极。该绝缘层形成在该衬底上，且该导电鳍形成在该绝缘层上。该导电鳍具有第一端，第二端以及位于该第一端与该第二端之间的中间部分，其中，该第一端与该第二端置于该绝缘层上，且中间部分与该绝缘层隔离。该电介质盖形成在该导电鳍的顶面上，栅极电介质层形成在该导电鳍的侧表面与底面上。该栅极形成在该绝缘层上，且该栅极围绕该导电鳍的中间部分的侧表面与底面。
本领域技术人员可在阅读说明书后，更了解本发明的其它好处或其它特征。所示的实施例说明实施本发明的最佳实施方式。可在不脱离本发明范围与精神的情况下，对本发明作各种显见的变更。因此，应将附图视为说明参考用，而非限制用。
附图说明
通过参照附图可更了解本发明上述的说明，附图中类似组件标有类似的参考符号。
图1显示了可用于形成本发明实施例的鳍的示例层的剖面图；
图2A显示了根据本发明的示范实施例所形成的鳍的剖面图；
图2B显示了根据本发明的示范实施例的图2A中半导体器件的俯视图；
图3A和图3B显示了根据本发明的示范实施例的位于图2A中鳍下的绝缘层底切的剖面图；
图4显示了根据本发明的示范实施例的位于图3B中鳍上的栅极电介质层的形成的剖面图；
图5显示了根据本发明的示范实施例的位于图4中器件上的栅极材料的形成的剖面图；
图6显示了根据本发明的示范实施例的栅极材料平坦化的剖面图；
图7显示了根据本发明的示范实施例形成的示例的双栅极器件的俯视图；
图8A至8E显示了根据本发明的示范实施例的多个鳍的形成的剖面图；以及
图9A和9B显示了根据本发明的示范实施例的突起源极/漏极区域的形成的剖面图。
具体实施方式
以下特定的具体实例将参考附图。不同附图中相同的参考符号代表相同或类似组件。并且，下列说明并非限制本发明，而由所附的权利要求书及其均等物来限定本发明的范畴。
按照本发明的实施例提供双栅极FinFET器件以及制造该种器件的方法。根据本发明所形成的FinFET器件可包括形成在导电鳍相对侧的栅极，且有栅极材料围绕该导电鳍的底面。
图1说明根据本发明实施例所形成的半导体器件100的剖面图。参考图1，半导体器件100可包括绝缘体上硅(silicon on insulator；SOI)的结构，其包括硅衬底110、埋入氧化层120、以及位于埋入氧化层120上的硅层130。埋入氧化层120以及硅层130可用传统的方式形成在衬底110上。
在一实施例中，埋入氧化层120可包括氧化硅并且可具有大约1500埃到3000埃的厚度。硅层130可包括单晶硅或多晶硅，并具有大约200埃到1000埃的厚度。硅层130可用于形成双栅极晶体管器件的鳍结构，如下的详细说明。
在本发明的另一实施例中，衬底110和硅层130可包括其它的半导体材料，例如，锗或半导体材料的组合物，如硅锗。埋入氧化层120也可包括其它的电介质材料。
电介质层140，如氮化硅层或氧化硅层，可形成在硅层130上作为后续蚀刻工艺时的保护罩。在一实施例中，可沉积电介质层140从大约100埃到250埃的厚度。接着，沉积并图形化光刻胶材料以形成后续工艺用的光刻胶掩膜150。可用传统方式沉积并图形化光刻胶材料。
接着可蚀刻半导体器件100。在一实施例中，可用传统方式蚀刻硅层130，蚀刻至埋入氧化层120即停止，如图2A所示。参考图2A，已蚀刻电介质层140以及硅层130并形成具有硅和电介质层140的鳍210。
在形成鳍210之后，源极和漏极区域可形成在鳍210的相邻的各端。例如，在一实施例中，可用传统方式沉积、图形化、以及蚀刻一层硅、锗或硅和锗的组合物来形成源极和漏极区域。图2B说明根据本发明的一实施例的半导体器件100的俯视图，该半导体器件100包括在埋入氧化层120上与鳍210相邻形成的源极区域220以及漏极区域230。
在形成源极区域220以及漏极区域230之后，可使用传统的化学蚀刻剂来蚀刻半导体器件100以去除部分的埋入氧化层120，如第3A图所示。在一实施例中，该蚀刻可去除大约100埃到250埃的埋入氧化层120。在蚀刻过程中，去除在鳍210下的埋入氧化层120的一部分，如图3A所示的区域300。可使用此鳍210下的横向底切以利于后续工艺中更进一步蚀刻鳍210下的埋入氧化层120。
可执行第二蚀刻以横向蚀刻通过鳍210下的埋入氧化层120的部分。在一实施例中，可执行例如高压下溴化氢(HBr)的各向同性蚀刻以横向蚀刻通过鳍210下的埋入氧化层120，如图3B所示。
图3B所示鳍210的剖面实际上悬空在埋入氧化层120上。但鳍210的端部仍连接至该埋入氧化层120，并且如图3B所示的鳍210的悬空部分由该埋入氧化层120在鳍210相邻源极/漏极区域220和230的各自的端部所支撑。
可去除该光刻胶掩膜150然后在鳍210上形成电介质层。例如，可在鳍210上热生长一层薄的氧化膜410，如图4所示。可生成大约厚度为10埃到30埃的氧化膜410，并形成在鳍210的暴露的硅侧表面及底面上，以作为栅极电介质层。但是该电介质层140保护鳍210的顶面。
接着可在半导体器件100上沉积硅层510，如图5所示。该硅层510可包括用于后续形成栅极电极的栅极材料。在一实施例中，该硅层510可包括用传统化学气相沉积(CVD)而得的厚度为500埃到1000埃的多晶硅。或者，可使用其它的半导体材料，如锗或硅和锗的组合物，或其它可作为栅极材料的不同金属。
然后可平坦化半导体器件100。例如，可执行化学机械剖光(CMP)使栅极材料(即，硅层510)与电介质层140在垂直方向齐平或接近齐平，如图6所示。参考图6，硅层510的剖面在半导体器件100的沟道区域为U型，并且栅极材料在沟道区域中的鳍210的两侧表面以及底面围绕鳍210。然而，电介质层140覆盖鳍210的顶面。
接着可图形化并蚀刻该硅层510以形成栅极电极。例如，图7说明了按照本发明的在栅极电极形成之后的半导体器件100的俯视图。如所述，半导体器件100包括具有栅极电极710和720以及围绕鳍210的底部分的栅极材料510(图6)的双栅极结构。为了简洁，图7没有示出围绕在鳍210的侧表面与底面的栅极电介质410。
接着可掺杂源极/漏极区域220和230。例如可将N型或P型掺杂物注入源极/漏极区域220和230。可视个别器件需要而选择特定的掺杂剂量与能量。本领域技术人员可根据电路需要将源极/漏极注入步骤最佳化，而为了不过分混淆本发明的要点，在此将不再赘述其工艺步骤。另外，可在源极/漏极离子注入之前选择性形成侧壁间隔体，以根据特定的电路需要来控制源极/漏极结的位置。接着可执行激活退火以激活该源极/漏极区域220和230。
图7所示的结果的半导体器件100为具有第一栅极710与第二栅极720的双栅极器件。该栅极材料510(图6)围绕鳍210的三个表面，并且与传统的FinFET比较，为半导体器件100提供每器件更多的沟道宽度，同时使鳍210能维持在栅极蚀刻时保护鳍210的电介质层140。此外，当需要第三栅极电极时，围绕鳍210底部分的栅极材料510可作为第三栅极。
在某些实施例中，可略过横向底切埋入氧化层120有关的步骤，如前图3A以及图3B所示的，这将产生两个电性与物理上分离的栅极电极710和720。在此情况时，当用于电路时，栅极电极710和720中的每一个皆可被分开偏压，因为实际上栅极电极710和720通过鳍210而互相分隔开。例如，在此情况时，根据特定电路需求可将栅极电极710用与栅极电极720不同的电压来偏压。在电路设计时，独立偏压的栅极增加半导体器件的灵活性。另外，栅极电极710可相对栅极电极720独立的被掺杂N型或P型掺杂物，以及反之亦然。
因此，根据本发明，可形成在器件的沟道区域具有U形剖面的双栅极FinFET器件。有利的是完成的结构具有良好的短沟道特性。并且，本发明提供更多灵活性并且很容易的整合至传统的工艺中。
其它实施例
在某些实施例中，FinFET可能需要多个鳍。图8A至图8E说明了形成多个鳍的示例工艺。图8A说明半导体器件800的剖面图。参考图8A，器件800可包括埋入氧化层(Buried oxide layer，BOX)810、鳍层820，二氧化硅(SiO2)层830，二氧化硅(SiO2-)结构840，以及多晶硅间隔体850。鳍层820可包括硅、锗或硅和锗组合物。可以传统的方式形成层810至830、结构840以及间隔体850。可根据将形成的鳍之间所需的距离而形成具有预定宽度的结构840以及间隔体850。
接着可蚀刻SiO2结构840以及SiO2层830，形成如同图8B所示的结构。如图所示，该多晶硅间隔体850保护下层的SiO2不被侵蚀。接着可去除多晶硅间隔体850，如图8C所示。然后可以传统的方式蚀刻鳍层820，该SiO2作为掩膜以保护其下方的鳍材料，如图8D所示。接着可蚀刻SiO2掩膜，蚀刻停止于硅鳍材料，而形成如图8E所示的两个鳍。依此，可形成相隔预定距离的两个或以上的鳍。
在其它实施例中，可能希望有具有突起的源极/漏极的FinFET。图9A以及图9B说明了示例工艺的形成具有突起的源极/漏极区域的FinFET的剖面。参考图9A，器件900包括BOX层910、硅层920、栅极930以及侧壁间隔体940。可以传统的方式形成这些层/结构。可将硅层920回蚀入源极/漏极区域，而残留近10％的硅。接着，可执行倾斜的源极/漏极注入以掺杂源极/漏极区域，如图9A的箭头所示。根据特定的电路需求源极/漏极离子注入可包括N型或P型掺杂物。
在源极/漏极注入之后，可执行硅层920的选择性外延生长(SEG)来升高源极/漏极区域的高度，如图9B所示。在此情况下，通过SEG工艺可注入源极/漏极区域注入物以在所需的位置形成源极/漏极(S/D)结，以提高源极/漏极区域的高度。在此情况下，得到的器件可具有减少的寄生源极/漏极电阻。
在前述的说明中，为了使本发明更易了解，已揭露多种特定细节，例如特定材料、结构、化学成分、步骤等。但是，可在不依照本文所揭露的特定细节来实施本发明。在其它例子中，为了不模糊本发明的目标并未对熟知的工艺结构作详细说明。
可利用传统的沉积技术来沉积根据本发明的半导体器件制造时所使用的电介质与导电层。例如，可利用金属化技术，如各种CVD方法，包括低压CVD(LPCVD)以及增强CVD(ECVD)。
本发明可应用于制造双栅极半导体器件，更具体地可应用于具有100纳米或更小的设计特征的FinFET器件。本发明可应用于多种半导体器件的形成，因此，为了不模糊本发明的目标并未对熟知的工艺结构作详细说明。在实施本发明时，可利用传统的光刻技术以及蚀刻技术，因此，将不在此赘述。
本说明书仅揭露本发明的最佳实施例以及其变化的数个示例。应了解到本发明可以多种结合和多种环境下来使用，但仍然在本发明的原理的范围内。

Claims (9)

1.一种半导体器件(100)，包括：
衬底(110)；
形成在该衬底(110)上的绝缘层(120)；
形成在该绝缘层(120)上的栅极(510)，该栅极(510)在该半导体器件(100)的沟道区域具有U型剖面；
具有多个侧表面、一顶面以及一底面的鳍(210)，其中在该半导体器件(100)的该沟道区域中该栅极(510)围绕该底面以及侧表面的整个高度；
形成在该鳍(210)的该顶面上的电介质层(140)；以及
形成在该鳍(210)的该侧表面与该底面上的栅极电介质层(410)。
2.如权利要求1所述的半导体器件(100)，其中该栅极(510)包括置于该鳍(210)的第一侧上的第一栅极电极(710)以及置于该鳍(210)的该第一侧的对侧上的第二栅极电极(720)。
3.如权利要求2所述的半导体器件(100)，其中围绕鳍(210)底面的该栅极(510)的部分包括有第三栅极。
4.如权利要求1所述的半导体器件(100)，其中该绝缘层(120)包括埋入氧化层(buried oxide layer)。
5.一种制造半导体器件(100)的方法，包括：
在衬底(110)上形成绝缘层(120)；
在该绝缘层(120)上形成鳍结构(210)，该鳍结构(210)具有多个侧表面、一顶面以及一底面；
在该鳍结构(210)的顶面上形成电介质层(140)；
形成源极和漏极区域(220、230)；
蚀刻该绝缘层(120)以横向底切位于该鳍结构(210)的底面下的该绝缘层(120)；
在该鳍结构(210)上沉积栅极材料(510)，该栅极材料(510)围绕该鳍结构(210)的底面与至少一部分的侧表面；
平坦化该沉积的栅极材料(510)，其中该平坦化的栅极材料在该半导体器件(100)的沟道区域具有U型剖面；以及
图形化并蚀刻该栅极材料(510)以在该鳍结构(210)的对侧形成第一和第二栅极电极(710、720)。
6.如权利要求5所述的方法，其中该蚀刻包括：
使用溴化氢(Hbr)横向底切位于该半导体器件(100)的沟道区域中的该绝缘层(120)。
7.一种半导体器件(100)，包括衬底(110)，形成在该衬底(110)上的绝缘层(120)，形成在该绝缘层(120)上的导电鳍(210)，形成在该导电鳍(210)的顶面上的电介质盖(140)；形成在该导电鳍(210)的侧表面与整个底面上的栅极电介质层(410)，该器件的特征在于：
该导电鳍(210)具有第一端，第二端以及位于该第一端与该第二端之间的中间部分，其中该第一端与该第二端置于该绝缘层(120)上，且该中间部分与该绝缘层(120)隔离；以及
形成在该绝缘层(120)上的栅极(510)，该栅极(510)围绕该导电鳍(210)的中间部分的整个侧表面和底面，其中该栅极(510)在该半导体器件(100)的沟道区域具有U型剖面。
8.如权利要求7所述的半导体器件(100)，其中该栅极(510)包括置于该导电鳍(210)的第一侧上的第一栅极电极(710)以及置于该导电鳍(210)的该第一侧的对侧上的第二栅极电极(720)。
9.如权利要求7所述的半导体器件(100)，其中该栅极(510)包括置于该导电鳍(210)的第一侧上的第一栅极电极(710)，置于该导电鳍(210)的该第一侧的对侧上的第二栅极电极(720)以及置于该导电鳍(210)的底侧上的第三栅极电极。
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Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8222680B2 (en) 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7148526B1 (en) * 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US7259425B2 (en) * 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960804B1 (en) 2003-08-04 2005-11-01 Hussman Corporation Semiconductor device having a gate structure surrounding a fin
US6876042B1 (en) 2003-09-03 2005-04-05 Advanced Micro Devices, Inc. Additional gate control for a double-gate MOSFET
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7064022B1 (en) * 2003-12-08 2006-06-20 Advanced Micro Devices, Inc. Method of forming merged FET inverter/logic gate
US7271444B2 (en) * 2003-12-11 2007-09-18 International Business Machines Corporation Wrap-around gate field effect transistor
US8217450B1 (en) 2004-02-03 2012-07-10 GlobalFoundries, Inc. Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7564081B2 (en) * 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7402856B2 (en) * 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US7439588B2 (en) * 2005-12-13 2008-10-21 Intel Corporation Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
US7396711B2 (en) 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070148926A1 (en) * 2005-12-28 2007-06-28 Intel Corporation Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US7449373B2 (en) 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
US7425500B2 (en) 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7435683B2 (en) * 2006-09-15 2008-10-14 Intel Corporation Apparatus and method for selectively recessing spacers on multi-gate devices
US20080097346A1 (en) * 2006-09-19 2008-04-24 Alcon, Inc. Trocar cannula
US7700470B2 (en) 2006-09-22 2010-04-20 Intel Corporation Selective anisotropic wet etching of workfunction metal for semiconductor devices
US7842579B2 (en) * 2007-01-22 2010-11-30 Infineon Technologies Ag Method for manufacturing a semiconductor device having doped and undoped polysilicon layers
US7838948B2 (en) * 2007-01-30 2010-11-23 Infineon Technologies Ag Fin interconnects for multigate FET circuit blocks
US7680553B2 (en) 2007-03-08 2010-03-16 Smp Logic Systems Llc Methods of interfacing nanomaterials for the monitoring and execution of pharmaceutical manufacturing processes
EP2156017B1 (de) 2007-05-12 2011-05-18 Tiefenbach Control Systems Gmbh Schiidsteuereinrichtung zur durchführung der ausbaufunktion einer ausbaueinheit beim strebausbau in einem bergwerk
US20090004231A1 (en) 2007-06-30 2009-01-01 Popp Shane M Pharmaceutical dosage forms fabricated with nanomaterials for quality monitoring
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100155801A1 (en) * 2008-12-22 2010-06-24 Doyle Brian S Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
US7999298B2 (en) * 2008-12-30 2011-08-16 Intel Corporation Embedded memory cell and method of manufacturing same
US8957482B2 (en) * 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8461015B2 (en) * 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8472227B2 (en) * 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US9484462B2 (en) * 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US9922878B2 (en) 2010-01-08 2018-03-20 Semiconductor Manufacturing International (Shanghai) Corporation Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing
CN102122645B (zh) 2010-01-08 2014-03-12 中芯国际集成电路制造(上海)有限公司 集成电路结构、其制造方法和使用方法
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US8174055B2 (en) 2010-02-17 2012-05-08 Globalfoundries Inc. Formation of FinFET gate spacer
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8637372B2 (en) * 2011-06-29 2014-01-28 GlobalFoundries, Inc. Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate
US8637930B2 (en) * 2011-10-13 2014-01-28 International Business Machines Company FinFET parasitic capacitance reduction using air gap
US9166049B2 (en) * 2014-03-07 2015-10-20 Stmicroelectronics, Inc. Method to enhance strain in fully isolated finFET structures
US9685501B2 (en) 2014-04-02 2017-06-20 International Business Machines Corporation Low parasitic capacitance finFET device
US9362362B2 (en) 2014-04-09 2016-06-07 International Business Machines Corporation FinFET with dielectric isolated channel
US9112032B1 (en) * 2014-06-16 2015-08-18 Globalfoundries Inc. Methods of forming replacement gate structures on semiconductor devices
US9318574B2 (en) 2014-06-18 2016-04-19 International Business Machines Corporation Method and structure for enabling high aspect ratio sacrificial gates
US9748394B2 (en) 2015-05-20 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a multi-portioned gate stack
US9722079B2 (en) 2015-10-15 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
WO2017189123A1 (en) 2016-04-25 2017-11-02 Applied Materials, Inc. Horizontal gate all around device nanowire air gap spacer formation
CN107799420A (zh) * 2016-09-05 2018-03-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
TWI790939B (zh) * 2022-03-09 2023-01-21 華邦電子股份有限公司 半導體元件及其形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300160B1 (en) * 1999-11-18 2001-10-09 Eastman Kodak Company Process for charge coupled image sensor with U-shaped gates
JP2002043581A (ja) * 2000-06-02 2002-02-08 Internatl Business Mach Corp <Ibm> デュアル／ラップ−アラウンド・ゲート電界効果トランジスタおよびその製造方法
US20020149031A1 (en) * 2001-04-12 2002-10-17 Samsung Electronics Co., Ltd. Semiconductor device having gate all around type transistor and method of forming the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302044A (ja) * 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5705405A (en) 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5801387A (en) * 1996-03-28 1998-09-01 Electron Processing Systems, Inc. Method of and apparatus for the electron beam treatment of powders and aggregates in pneumatic transfer
JPH09293793A (ja) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5981367A (en) * 1996-10-17 1999-11-09 Micron Technology, Inc. Method for making an access transistor
JPH10163166A (ja) * 1996-11-28 1998-06-19 Mitsubishi Electric Corp 半導体装置の製造方法及び製造装置
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
US6544848B1 (en) * 2002-08-20 2003-04-08 Chartered Semiconductor Manufacturing Ltd. Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300160B1 (en) * 1999-11-18 2001-10-09 Eastman Kodak Company Process for charge coupled image sensor with U-shaped gates
JP2002043581A (ja) * 2000-06-02 2002-02-08 Internatl Business Mach Corp <Ibm> デュアル／ラップ−アラウンド・ゲート電界効果トランジスタおよびその製造方法
US20020149031A1 (en) * 2001-04-12 2002-10-17 Samsung Electronics Co., Ltd. Semiconductor device having gate all around type transistor and method of forming the same

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JP2006504268A (ja) 2006-02-02
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US6833588B2 (en) 2004-12-21
WO2004038804A3 (en) 2004-06-10
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TW200414324A (en) 2004-08-01
CN1708855A (zh) 2005-12-14
US20050006666A1 (en) 2005-01-13
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WO2004038804A2 (en) 2004-05-06
DE10393565B4 (de) 2010-07-15
US7179692B2 (en) 2007-02-20
GB0506579D0 (en) 2005-05-04
GB2409575A (en) 2005-06-29
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