TWI321336B - Semiconductor device having u-shaped gate structure - Google Patents

Semiconductor device having u-shaped gate structure Download PDF

Info

Publication number
TWI321336B
TWI321336B TW092128797A TW92128797A TWI321336B TW I321336 B TWI321336 B TW I321336B TW 092128797 A TW092128797 A TW 092128797A TW 92128797 A TW92128797 A TW 92128797A TW I321336 B TWI321336 B TW I321336B
Authority
TW
Taiwan
Prior art keywords
gate
fin
semiconductor device
insulating layer
layer
Prior art date
Application number
TW092128797A
Other languages
English (en)
Other versions
TW200414324A (en
Inventor
Bin Yu
Shibly S Ahmed
Judy Xilin An
Srikanteswara Dakshina-Murthy
Zoran Krivokapic
Haihong Wang
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200414324A publication Critical patent/TW200414324A/zh
Application granted granted Critical
Publication of TWI321336B publication Critical patent/TWI321336B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Description

1321336 疚、發明說明 【發明所屬之技術領域】 本發明係有關於半導體裝置以及製造半導體裝置的方 法’更詳而言之，係應用於雙閘極結構。 【先前技術】 超大型積體電路半導體裝置日益攀升之高密度與性能 需求需要例如閘極長度小於1 00奈米之設計特徵、高可靠 度以及更咼的製造生產能力。縮減設計特徵小於100奈 米之需求挑戰傳統方式的限制。 例如’當習知平面金屬氧化物半導體場效電晶體 (MOSFET)之閘極長度縮小於⑽奈米時，短通道效應的問 題’例如源極與汲極間之過量的漏電，變得更難克服。並 且移動性的降低以及其他若干製程問題亦使得調整習知 MOSFET以包含更小元件之困難度更大。因此需要發展新 裝置結構以增進FET性能並允許更進一步的裝置尺寸調 整。 _ 雙閘極MOSFET視為代表超越舊有平面式m〇sfet 之候選者的新結構。雙閘極M0SFET中，可用兩個閘極控 帝J短通道效應。鑛式場效電晶體（FinjpET)為近來雙閘極结 構之一種，並具有良好的短通道性能。FinFET包括形成於 垂直鰭型之通道。可使用類似習知平面式M〇SFET之佈局 以及製程技術製造FinFET結構。 【發明内容】 利用符合本發明之實施方式提供具有形成於導電鰭之 92450(修正版) 6 1321336 相對側之兩閘極的FinFET裝置。該裝置可包括位於導電 韓下的閘極材料以增加裝置之總通道寬。 本發明之額外的優點以及其他特徵將部份的於下述說 明，而熟悉該項技藝者透過閱讀下述說明或由實施本發明 亦能使本發明之優點以及特徵部份的更顯而易見。由所附 之申請專利範圍之指定可達成本發明之優點以及特徵。 根據本發明，可藉由包括有基板、絕緣層、第—閘極、 以及鰭（fln)之半導體裝置來部分的獲得上述以及其他好 處。該絕緣層形成於該基板上，且該第—閘極形成於該絕 緣層上。該第一閘極於半導體裝置之通道區域具有口型剖 面。該鰭具有複數個側表面、一頂面、以及一底面，其中 該第一閘極圍繞該底面以及至少部份的側表面。 根據本發明之另一態樣，提供一種製造半導體裝置的 方法。該方法包括形成絕緣層於基板上並形成鰭結構於該 絕緣層上。該鰭結構具有複數個侧表面、一頂面、以及一 底面。該方法亦包括形成電介質層於該鰭結構之頂面上， 形成源極和汲極區域並蝕刻該絕緣層以橫向底切（undercut) 位於該鰭結構底面下之絕緣層。該方法復包括沉積閘極材 料，該鰭結構上，纟中閘極材料圍繞該鰭結構之底面以及 至夕。卩伤的側表面。該方法另包括將沉積之閘極材料平坦 化、圖案化與姓刻該閉極材料以在該韓結構之相對側形成 第一和第二閘極電極。 根據本發明之又一態樣，提供一種半導體裝置，包括 有基板、絕緣層、導電韓、電介質蓋、閘極電介質層、以 92450(修正版) 7 3極該、..邑緣層形成於該基板上，且該導電縛形成於該 、·邑緣層上。該導電鰭具有第一端、第二端以及位在該第一 端與該第二端之中間部分，纟中，該第一端與該第二端置 於該絕緣層上’且中間部分與該絕緣層隔離。該電介質蓋 形成於該導電鰭之頂面上，以及閘極電介質層形成於該導 電鰭之侧表面與底面上。該閘極形成於該絕緣層上，且該 閘極圍繞該導電鰭之中間部分的側表面與底面。 熟知此技術者可在閱讀說明書後，更了解本發明的其 ㈣處或其他特徵。所示之實施例說明實施本發明之最佳 實施T式。可對本發明作各種顯見之變更而無法脫離本發 月之範圍與精神。因此，應視圖示為說明參考肖，而非限 制用。 【實施方式】 乂下特疋的具體實例將參考所附之圖示。不同圖示中 相同的參考苻號代表相同或類似元件。並且，下列說明並 非限制本發明’而由所附之申請專利範圍以及其均等物來 限定本發明之範疇。 符合本發明之實施例提供雙閘極FinFET裝置以及製 3種裝置的方法。根據本發明所形成之FinFET裝置可 括形成於導電鰭相對側之閘極，且有閘極材料圍繞該導 電韓之底面。 第1圖說明根據本發明一實施例所形成之半導體裝置 100的剖面圖。參考第1圖，半導體裝置100可包括矽覆 絕緣層（Silicon 〇n insulat〇r; s〇I)的結構，其包括矽基板 8 92450(修正版) 1321336 月知修胃 110、埋入氧化物層120、以及位在埋入氧化物層12〇上的 矽層130 ^埋入氧化物層120以及矽層13〇可用習知的方 式形成於基板110上。 在一實施例中，埋入氧化物層120可包括氧化矽並且 可具有大約2 500 A到3000 A的厚度。矽層130可包括單 晶矽或多晶矽，並具有大約200 A到1000 A的厚度。矽 層130可用於形成雙閘極電晶體裝置的鰭結構，如下之詳 細說明。 本發明之另一實施例中，基板110和矽層130可包括 其他半導體材料，例如，鍺、或半導體材料之組合 (combination)(如石夕鍺（silicon_germanium))。埋入氧化物 層120亦可包括其他電介質材料。 電介質層140,如氮化矽層或氧化矽層，可形成於矽 層130上作為後續蝕刻製程時的保護罩。在一實施例中， 可沉積電介質層140自大約100 Λ到25〇 A的厚度。接著， 沉積並圖案化光阻材料以形成後續製程用的光阻遮罩 150。可用習知方式沉積與圖案化光阻材料。 接著可姓刻半導體裝置100。在一實施例中，可.用習 知方式蝕刻矽層130，蝕刻至埋入氧化物層12〇即停止， 如第2A圖所示。參考第2A圖’已蝕刻電介質们4〇以及 矽層130並形成具有矽及電介質蓋mo之鰭21〇。 形成鰭2 I 0之後，源極和汲極區域可形成於鰭2】〇之 相鄰的分別端。例如，在一實施例中，可用習知方式沉積、 圖案化、以及蝕刻一層矽 '鍺或矽和鍺之组合來形成源極 (修正頁)92450 9 13213^0 和没極區域1 2B圖說明根據本發明之—實施例之半導 體裝置100的俯視圖，兮主道脚 圆这牛導體裝置100包括於埋入氧化 物層120上與n 21M目鄰形成之源極區域22〇以及没極區 域 230 〇 形成源極區域220以及汲極區域230之後，可使用習 知的化學钱刻劑钮刻半導體裝置1〇〇以移除部分的埋入氧 化物層120如第3 A圖所示。在一實施例中，該蝕刻可移 除大，，、勺1 GO A到2 5 G A的埋人氧化物層i 2 Q。在姓刻過程 中，移除在鳍210下一部份的埋入氧化物層12〇，如第3A 圖所示之區域300。可使用此鰭21〇下之橫向底切以利於 後續製程中更進一步蝕刻鰭21〇下之埋入氧化物層12〇。 了執行第一银刻以橫向姓刻通過鰭21〇下之埋入氧化 物層120的部分。在一實施例中，可執行例如高壓下溴化 鼠（HBr)之荨向性钱刻以橫向姓刻通過韓2 1 〇下之埋入氧 化物層120，如第3B圖所示。 第3B圖所示鰭21〇之剖面實際上係懸空於埋入氧化 物層120上。但鰭21〇之端部連接至該埋入氧化物層12〇, 以及如第3B圖所示之鰭21〇之懸空部分由該埋入氧化物 層120於鰭21〇相鄰源極/汲極區域22〇和23〇之分別的端 部所支撐。 可移除該光阻遮罩150然後於鰭210上形成電介質 層°例如’可在鰭210上熱生成一層薄的氧化物薄膜410, 如第4圖所示。可生成大約厚度為ι〇Α到3〇 a之氧化物 薄膜410並形成於鰭21〇之暴露的矽側表面及底面上，以 10 92450(修正版) 作為閉極電介質層。作B兮 疋绞電介質蓋290保護鰭21〇之了頁 面。 接著可沉積矽層510於半導 卞守菔裒置100上，如第5圖 所示。該矽層510可包括用 铋 „ 。括用於後續形成閘極電極之間極材 料。在-實施例中，該…〇可包括用 積(CVD)而得之厚度為的多晶^:者： 可使用其他半導體材料，如铋、 ^如鍺、或矽和鍺之組合，或其 可作為閘極材料之不同金屬。 、 然後可平坦化半導體梦署彳π 裝置1 00。例如，可執行化學機 械研磨（CMP)使閘極材料（亦 何計（丌即矽層5丨〇)與電介質蓋290在 向齊平或接近齊平，如第6圖所示。參考第6圖， 石夕層51〇之剖面於半導體裝£刚之通道區域為㈣，並 且閘極材料圍繞鰭2】0於通道區域中之兩側表面以及底 面。然而’電介質蓋290覆蓋鰭210之頂面。 接考可圖案化並餘刻該石夕層51〇以形成問極電極。例 第圖。兑明符合本發明於閘極電極形成後半導體裝置 1〇0之俯視圖。如所述，半導體裝置⑽包括具有閘極電 極710和720以及圍繞韓21〇之底部分的閘極材料5叫第 6圖）之雙間極結構。為了簡潔，第7圖未示出圍繞於韓2】〇 之側表面與底面之閘極電介質4 1 0。 著1"彳雜源極/没極區域2 2 0和2 3 0。例如可佈植 (imPlant)n型或Ρ型雜質入源極/汲極區域220和230。可 、, 別裝且需要選擇特定的佈值劑量與能量。熟悉該項技 術θ可根據電路需要將源極/汲極佈值步驟最佳化，而為了 (修正頁)92450 11 1321336
日修⑻正替換頁 不過分混淆本發明之要點，在此將不再贅述其製程步驟。 另外，可於源極/汲極離子佈值前選擇性形成側壁間隔體 (sidewall spacer)以根據特定電路需要控制源極/汲極接面 位置。接者可執行活化退火（activati〇n annealing)以活化該 源極/沒極區域220和230。 第7圖所示之結果的半導體裝置為具有第一閘極71〇 與第二閘極720之雙閘極裝置。該閘極材料51〇(第6圖） 圍繞縛210之三個表面，並且與習知FinFET比較，提供 半導體裝置100每裝置更多的通道寬度，同時使鰭21〇能 維持於閘極蝕刻時保護鰭2丨〇之電介質蓋29〇。又，杏
、 田 TTTJ 要第三閘極電極時，圍繞鰭210底部分之間極材料51〇可 作為第三閘極。 於某些貝％例中，可略過橫向底切埋入氧化物層工2 〇 有關之步驟，如前苐3八圖以及第33圖所示者，這將產生 兩個電性與物理上分離之閘極電極7丨〇和72〇。於此情況 ，^當使用於電路時，閘極電極71〇和72〇中之每一個皆 :分開偏壓，因為實際上閘極電極71〇和72〇藉由鰭21〇 與相刀隔開。例如，於此情況時，可將閘極電極7! 〇用 於I據特疋f路需求之閘極電極720不同的電愿來偏1。 性电路叹计時’獨立偏麼之閉極增加半導體裝置的靈活 。另外，可相對閘極電極720獨立摻雜n型或p型雜質 甲極電極7 1 〇，以及反之亦然。 :此，根據本發明，可形成在裝置之通道區域具有u 之㈣極…服裝置。有利的係完成之結構具有 (修正頁)92450 12 1321336 良好的短通道行為。並且，本發明提供更多靈活性並且很 容易的整合至習知的製程。 其他實施你丨 在某些實施例中，FinFET可能需要數個縛。第8A圖至第 8E圖說明形成數個鰭之範例製程。第8八圖說明半導體裝 置800之剖面圖。參考第8八圖，裝置8〇〇可包括埋入氧 化物層（Buried oxide layer，Β〇χ 層）81〇、鰭層 82〇，二氧 化矽（SiCh)層830，二氧化矽（Si〇2)結構84〇，以及多晶矽 間隔體850。鰭層820可包括矽、鍺、或矽和鍺之組合。 可以習知方式形成層810至830 '結構84〇以及間隔體 850。可根據將形成之鰭之間所需之距離而形成具有預定寬 度之結構840以及間隔體850。 接著可蝕刻SiCh結構840以及Si〇2層83〇形成如同 第8B圖所示之結構。如圖所示，該多晶矽間隔體85〇保 護下層之si〇2不被侵蝕。接著可移除多晶矽間隔體85〇， 如第8C圖所示。然後可以習知方式蝕刻鰭層82〇，該si〇2 作為遮罩以保護其下方之鰭材料，如第8D圖。接著可姓 刻Si〇2遮罩，蝕刻停止於矽鰭材料，而形成如第8E圖所 示之兩鰭。依此’可形成相隔預定距離之兩個或以上之韓。 在其他實施例中，可能希望有具有突起之源極/汲極之 FinFET。第9A圖以及第9B圖說明範例製程之形成具有突 起之源極/汲極區域之FinFET之剖面。參考第9A圖，事 置900包括BOX層910、矽層920、閘極93〇以及側壁間 隔體940。可以習知方式形成這些層/結構。可將石夕層92〇 92450(修正版) 13 1321336 回蝕入源極/汲極區域而殘留近i 0%的矽。接著，可執行傾 斜之源極/汲極佈值以摻雜源極/汲極區域，如第9A圖之箭 頭所示。根據特定電路需求源極/汲極離子佈值可包括η型 或Ρ型雜質。 在源極/汲極佈值之後，可執行矽層920之選擇性磊晶 成長（Selective Epitaxial Growth; SEG)來升高源極 /沒極區 域之南度’如第9B圖所示。在此情況下，藉由SEG步驟 可佈值源極/汲極區域佈值物以在所需之位置形成源極/汲 極（S/D)接面，以提高源極/汲極區域之高度。在此情況下， 得到的裝置可具有減少的寄生源極/汲極電阻。 在前述之說明中’為了使本發明更易了解，已揭露多 種特定細節，例如特定材料、結構、化學成分、步驟等。 惟，可在不依照本文所揭露之特定細節來實施本發明。在 其他例子中，為了不模糊本發明之目標並未對熟知的製程 結構作詳細說明。 可利用習知的沉積技術來沉積根據本發明之半導體裝 置製造時所使用的電介質與導電層。例如，可利用金屬化 技術，如各種CVD方法，包括低壓CVD(LpcVD)以及增 強 CVD(ECVD)。 本發明可應用於製造雙閘極半導體裝置，以及更詳言 之可應用於具有設計特徵1〇〇奈米或更小之FinFET裝 置。本發明可應用於多種半導體裝置的形成，因此，為了 不模糊本發明之目標並未對熟知#製程結構作詳細說明。 於實施本發明_，可利用習知光學微影技術以及餘刻技 14 92450(修正版) 術’因此’將不在此贅述。 本說明書僅揭露本發明之最佳實施例以及其變化之數 個範例。冑了解到本發明可以多種結合和多種環境下來使 用’但仍然在本發明之原理的範圍内。 【圖式簡單說明】 _藉由參照所附之圖示可更了解本發明上述之說明，圖 示中類似元件標有類似的參考符號。 第1圖顯不-可用於形成本發明之鱗之範例層的剖面 圖； 第2A圖顯不根據本發明之示範實施例所形成之韓的 剖面圖； 第2B圖顯不根據本發明之示範實施例之第μ圖半導 體裝置之俯視圖； 第3A圖以及第3B圖顯示根據本發明之示範實施例之 第2A圖位於鰭下之絕緣層底切之剖面圖； 第4圖顯不根據本發明之示範實施例之第化圖位於 鳍上之閘極電介質層的形成之剖面圖； 第5圖顯不根據本發明之示範實施例之第*圖於裝置 上閘極材料之形成之剖面圖； 第6圖顯不根據本發明之示範實施例t閘極材料平坦 化之剖面圖； 第7圖顯不根據本發明之示範實施例形成之範例雙閘 極裝置之俯視圖； 第8A至8E圖題千ip诚· 士 β 喷不根據本發明之示範實施例複數鰭之 92450(修正版) 15 1321336 形成的剖面圖；以及 第9A圖以及第9B厫批_ , 突起源極/汲㈣域之形‘“，4據本發明之示範實施例的 /攻的到面圖。 【主要元件符號說明】 100 半導體裝置 110 矽基板 120 埋入氧化物層 130 秒層 140 電介質層 150 光阻遮罩 210 韓 220 源極區域 230 汲極區域 300 面積 410 閘極電介質、氧化物薄联 510 矽層 '閘極材料、閘極 710、 7 2 0閘極電極 800 820 半導體裝置 鋒層 810 埋入氧化物層(ΒΟχ層) 830 Si02 層 840 Si〇2結構 850 間隔體 900 裝置 910 BOX層 920 矽層 930 閘極 940 侧壁間隔體 290 電介質蓋 (修正頁)92450 16

Claims (1)

1321336 附件3 ?ΛΤ8號月專1, 拾、申請專利範圍： 1. 一種半導體裝置（100)，包括： 基板（110); 形成於該基板（110)上之絕緣層（12〇); 形成於該絕緣層（1 20)上的第一閘極（5〗〇)，該第— 閘極（5 10)於該半導體裝置（1〇〇)之通道區域具有υ型剖 面，以及 具有複數個側表面、頂面以及底面之鰭（2丨〇)，其 中該第一閘極（5 10)圍繞該底面與至少部份的該等側表 面。 2. 如申請專利範圍第1項之半導體裝置（1〇〇)，復包括： 形成於該絕緣層（1 2 0)上位在該鰭之與該第—閘極 (710)相對的側的第二閘極（720)。 3·如申請專利範圍第2項之半導體裝置（100)，其中圍繞 該鰭（210)之底面之該第一閘極（51〇)的部分包括第三閘 極。 4. 如申請專利範圍第1項之半導體裝置（1〇〇)，其中該絕 緣層（120)包括埋入氧化物層（buriecj 〇xide layer)。 5. —種製造半導體裝置（loo)之方法，包括： .形成絕緣層（120)於基板（11〇)上； 形成鰭結構（210)於該絕緣層（120)上，該鰭結構 (21 0)具有複數個側表面、項面以及底面； 形成電介質層（140)於該鰭結構（210)之該頂面上； 形成源極和汲極區域（220、230); 17 (修正本)92450 1321336 第92128·79·?號專利申請案 (9 8年8月 3日） 姓刻該絕緣層（120)以橫向底切位於該鰭結構（210) 之該底面下之該絕緣層（]2〇); 於該韓結構（2 10)上沉積閘極材料（51〇)，該閘極材 料（5 10)圍繞該鰭結構（2 1〇)之該底面與至少部份的該 等側表面； 平坦化該沉積之閘極材料（5〗〇);以及 圖案化與姓刻該閘極材料（5 1 0)以於該鰭結構（2 1 〇) 之相對側形成第一和第二閘極電極（7丨〇、72〇)。 6. 如申請專利範圍第5項之方法，其中該蝕刻包括： 使用溴化氫（HBr)橫向底切位於該半導體裝置（1 〇〇) 之通道區域中之該絕緣層（12〇)。 7. —種半導體裝置（100)，包括基板（11〇)、形成於該基板 (110)上之絕緣層（120) '形成於該絕緣層（12〇)上之導電 鰭（210)、形成於該導電鰭（21〇)之頂面上之電介質蓋 (2 9 0 );形成於該導電鰭（2 I 〇)之側表面 電介質層⑷〇)，該裝置的特徵在於：該導電趙（21= 有第一端、第二端以及位在該第—端與該第二端之間的 中間部分，其中，該第一端與該第二端置於該絕緣層 U20)上，且該中間部分與該絕緣層（12G)隔離；以及 形成於該絕緣層（120)上之閘極（510)，該閑極（510) 圍繞該導電籍（2丨0)之該中間部分的側表面與底面。 8. 如申請專利範圍第7項之半導體裝置〇〇〇)，其中該閘 極（510)於該半導體裝置（1〇〇)之通道區域具有口型剖 面。 (修正本)92450 18 第 92128797 < 9 8 年 8 丄321336 9.如申請專利範圍第7項之半導體裝置（⑽），其 極（5 10)包括置於該導電鰭（21〇)之第一側上的第 電極（7】0)以及置於該導電鰭（21〇)之相對側上的 極電極（720卜 】〇·如申請專利範圍第7項之半導體裝置（1〇〇)，其 .極（5】〇)包括置於該導電鰭（21〇)之第一側上的$ 極電極（710)、置於該導電鰭（21〇)之相對侧上的 極電極（720)以及置於該導電鰭（21〇)之底側上的 極電極。 號專利申請索 月3曰） 中該閘 一閘極 第二閘 中該閘 !—閘 第二閘 第三閘 19 (修正本)92450
TW092128797A 2002-10-22 2003-10-17 Semiconductor device having u-shaped gate structure TWI321336B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/274,867 US6833588B2 (en) 2002-10-22 2002-10-22 Semiconductor device having a U-shaped gate structure

Publications (2)

Publication Number Publication Date
TW200414324A TW200414324A (en) 2004-08-01
TWI321336B true TWI321336B (en) 2010-03-01

Family

ID=32093167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092128797A TWI321336B (en) 2002-10-22 2003-10-17 Semiconductor device having u-shaped gate structure

Country Status (9)

Country Link
US (2) US6833588B2 (zh)
JP (1) JP4745663B2 (zh)
KR (1) KR100993937B1 (zh)
CN (1) CN100448023C (zh)
AU (1) AU2003282849A1 (zh)
DE (1) DE10393565B4 (zh)
GB (1) GB2409575B (zh)
TW (1) TWI321336B (zh)
WO (1) WO2004038804A2 (zh)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8222680B2 (en) 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7148526B1 (en) 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US7259425B2 (en) * 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6960804B1 (en) 2003-08-04 2005-11-01 Hussman Corporation Semiconductor device having a gate structure surrounding a fin
US6876042B1 (en) 2003-09-03 2005-04-05 Advanced Micro Devices, Inc. Additional gate control for a double-gate MOSFET
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7064022B1 (en) * 2003-12-08 2006-06-20 Advanced Micro Devices, Inc. Method of forming merged FET inverter/logic gate
US7271444B2 (en) * 2003-12-11 2007-09-18 International Business Machines Corporation Wrap-around gate field effect transistor
US8217450B1 (en) 2004-02-03 2012-07-10 GlobalFoundries, Inc. Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7564081B2 (en) * 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7402856B2 (en) * 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US7439588B2 (en) * 2005-12-13 2008-10-21 Intel Corporation Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
US7396711B2 (en) 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070148926A1 (en) * 2005-12-28 2007-06-28 Intel Corporation Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
US7425500B2 (en) 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US7449373B2 (en) 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7435683B2 (en) * 2006-09-15 2008-10-14 Intel Corporation Apparatus and method for selectively recessing spacers on multi-gate devices
US20080097346A1 (en) * 2006-09-19 2008-04-24 Alcon, Inc. Trocar cannula
US7700470B2 (en) 2006-09-22 2010-04-20 Intel Corporation Selective anisotropic wet etching of workfunction metal for semiconductor devices
US7842579B2 (en) * 2007-01-22 2010-11-30 Infineon Technologies Ag Method for manufacturing a semiconductor device having doped and undoped polysilicon layers
US7838948B2 (en) * 2007-01-30 2010-11-23 Infineon Technologies Ag Fin interconnects for multigate FET circuit blocks
US7680553B2 (en) * 2007-03-08 2010-03-16 Smp Logic Systems Llc Methods of interfacing nanomaterials for the monitoring and execution of pharmaceutical manufacturing processes
DE112008001189A5 (de) 2007-05-12 2010-01-28 Tiefenbach Control Systems Gmbh Schildsteuereinrichtung zur Durchführung der Ausbaufunktion einer Ausbaueinheit beim Strebausbau in einem Bergwerk
US20090004231A1 (en) 2007-06-30 2009-01-01 Popp Shane M Pharmaceutical dosage forms fabricated with nanomaterials for quality monitoring
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100155801A1 (en) * 2008-12-22 2010-06-24 Doyle Brian S Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
US7999298B2 (en) * 2008-12-30 2011-08-16 Intel Corporation Embedded memory cell and method of manufacturing same
US8957482B2 (en) * 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8461015B2 (en) * 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8472227B2 (en) * 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US9922878B2 (en) 2010-01-08 2018-03-20 Semiconductor Manufacturing International (Shanghai) Corporation Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing
CN102122645B (zh) 2010-01-08 2014-03-12 中芯国际集成电路制造(上海)有限公司 集成电路结构、其制造方法和使用方法
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US8174055B2 (en) 2010-02-17 2012-05-08 Globalfoundries Inc. Formation of FinFET gate spacer
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8637372B2 (en) * 2011-06-29 2014-01-28 GlobalFoundries, Inc. Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate
US8637930B2 (en) * 2011-10-13 2014-01-28 International Business Machines Company FinFET parasitic capacitance reduction using air gap
US9166049B2 (en) * 2014-03-07 2015-10-20 Stmicroelectronics, Inc. Method to enhance strain in fully isolated finFET structures
US9685501B2 (en) 2014-04-02 2017-06-20 International Business Machines Corporation Low parasitic capacitance finFET device
US9362362B2 (en) 2014-04-09 2016-06-07 International Business Machines Corporation FinFET with dielectric isolated channel
US9112032B1 (en) * 2014-06-16 2015-08-18 Globalfoundries Inc. Methods of forming replacement gate structures on semiconductor devices
US9318574B2 (en) * 2014-06-18 2016-04-19 International Business Machines Corporation Method and structure for enabling high aspect ratio sacrificial gates
US9748394B2 (en) 2015-05-20 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a multi-portioned gate stack
US9722079B2 (en) 2015-10-15 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
JP6780015B2 (ja) 2016-04-25 2020-11-04 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 水平ゲートオールアラウンドデバイスのナノワイヤの空隙スペーサ形成
CN107799420A (zh) * 2016-09-05 2018-03-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
TWI790939B (zh) * 2022-03-09 2023-01-21 華邦電子股份有限公司 半導體元件及其形成方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302044A (ja) * 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5273921A (en) * 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5705405A (en) * 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5801387A (en) * 1996-03-28 1998-09-01 Electron Processing Systems, Inc. Method of and apparatus for the electron beam treatment of powders and aggregates in pneumatic transfer
JPH09293793A (ja) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5981367A (en) * 1996-10-17 1999-11-09 Micron Technology, Inc. Method for making an access transistor
JPH10163166A (ja) * 1996-11-28 1998-06-19 Mitsubishi Electric Corp 半導体装置の製造方法及び製造装置
US6300160B1 (en) * 1999-11-18 2001-10-09 Eastman Kodak Company Process for charge coupled image sensor with U-shaped gates
US6563131B1 (en) 2000-06-02 2003-05-13 International Business Machines Corporation Method and structure of a dual/wrap-around gate field effect transistor
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
KR100414217B1 (ko) * 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6544848B1 (en) * 2002-08-20 2003-04-08 Chartered Semiconductor Manufacturing Ltd. Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers

Also Published As

Publication number Publication date
GB2409575B (en) 2006-02-15
US6833588B2 (en) 2004-12-21
CN1708855A (zh) 2005-12-14
JP4745663B2 (ja) 2011-08-10
TW200414324A (en) 2004-08-01
AU2003282849A1 (en) 2004-05-13
DE10393565T5 (de) 2005-09-01
US20040075121A1 (en) 2004-04-22
DE10393565B4 (de) 2010-07-15
WO2004038804A2 (en) 2004-05-06
GB2409575A (en) 2005-06-29
GB0506579D0 (en) 2005-05-04
US20050006666A1 (en) 2005-01-13
KR100993937B1 (ko) 2010-11-12
KR20050057663A (ko) 2005-06-16
CN100448023C (zh) 2008-12-31
JP2006504268A (ja) 2006-02-02
WO2004038804A3 (en) 2004-06-10
US7179692B2 (en) 2007-02-20

Similar Documents

Publication Publication Date Title
TWI321336B (en) Semiconductor device having u-shaped gate structure
KR101079348B1 (ko) ＦｉｎＦＥＴ 디바이스에 게이트를 형성하고 ＦｉｎＦＥＴ디바이스의 채널 영역의 핀을 가늘게 하는 방법
US7449733B2 (en) Semiconductor device and method of fabricating the same
US10283640B2 (en) Source/drain contacts for non-planar transistors
US7259425B2 (en) Tri-gate and gate around MOSFET devices and methods for making same
EP1554758B1 (en) Methods for making double and triple gate mosfet devices
US7256455B2 (en) Double gate semiconductor device having a metal gate
TWI253175B (en) FinFET transistor device on SOI and method of fabrication
KR101369134B1 (ko) 나노와이어 메시 디바이스와 그 제조 방법
US7723196B2 (en) Damascene gate field effect transistor with an internal spacer structure
EP2270868B1 (en) Methods of fabrication of a nonplanar semiconductor device with partially or fully wrapped around gate electrode
JP3974837B2 (ja) 二重ゲート・トランジスタおよびその製造方法
US6709982B1 (en) Double spacer FinFET formation
TWI396284B (zh) 場效電晶體及其製造方法
US6406945B1 (en) Method for forming a transistor gate dielectric with high-K and low-K regions
US20050285186A1 (en) Semiconductor device and method of fabricating the same
TW200414326A (en) Planarizing gate material to improve gate critical dimension in semiconductor devices
TW200908331A (en) Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
US20160260741A1 (en) Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US7041601B1 (en) Method of manufacturing metal gate MOSFET with strained channel
TWI828028B (zh) 半導體裝置及其製造方法
US20090001474A1 (en) Semiconductor device with reduced fringe capacitance
TW202123422A (zh) 半導體結構

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent