CN100446225C - 具有内装芯片和两侧上的外部连接端子的基板及其制造方法 - Google Patents

具有内装芯片和两侧上的外部连接端子的基板及其制造方法 Download PDF

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Publication number
CN100446225C
CN100446225C CNB2005101315584A CN200510131558A CN100446225C CN 100446225 C CN100446225 C CN 100446225C CN B2005101315584 A CNB2005101315584 A CN B2005101315584A CN 200510131558 A CN200510131558 A CN 200510131558A CN 100446225 C CN100446225 C CN 100446225C
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China
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built
substrate
semiconductor chip
external connection
resin member
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Expired - Fee Related
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English (en)
Chinese (zh)
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CN1819160A (zh
Inventor
山野孝治
荒井直
町田洋弘
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Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
CNB2005101315584A 2004-10-22 2005-09-21 具有内装芯片和两侧上的外部连接端子的基板及其制造方法 Expired - Fee Related CN100446225C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004308558A JP2006120943A (ja) 2004-10-22 2004-10-22 チップ内蔵基板及びその製造方法
JP2004308558 2004-10-22

Publications (2)

Publication Number Publication Date
CN1819160A CN1819160A (zh) 2006-08-16
CN100446225C true CN100446225C (zh) 2008-12-24

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CNB2005101315584A Expired - Fee Related CN100446225C (zh) 2004-10-22 2005-09-21 具有内装芯片和两侧上的外部连接端子的基板及其制造方法

Country Status (6)

Country Link
US (1) US7312536B2 (https=)
EP (1) EP1650798A3 (https=)
JP (1) JP2006120943A (https=)
KR (1) KR20060051422A (https=)
CN (1) CN100446225C (https=)
TW (1) TW200614900A (https=)

Cited By (1)

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CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

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JP4428337B2 (ja) * 2005-12-02 2010-03-10 ソニー株式会社 半導体装置の製造方法
KR100770874B1 (ko) 2006-09-07 2007-10-26 삼성전자주식회사 매설된 집적회로를 구비한 다층 인쇄회로기판
KR100823699B1 (ko) * 2006-11-29 2008-04-21 삼성전자주식회사 플립칩 어셈블리 및 그 제조 방법
US8178982B2 (en) * 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
JP2008277639A (ja) * 2007-05-02 2008-11-13 Casio Comput Co Ltd 半導体装置およびその製造方法
US9610758B2 (en) 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
KR100929464B1 (ko) * 2007-12-21 2009-12-02 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 반도체칩 적층 패키지
JP4787296B2 (ja) 2008-07-18 2011-10-05 Ｔｄｋ株式会社 半導体内蔵モジュール及びその製造方法
US8390083B2 (en) 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
WO2011155638A1 (en) * 2010-06-11 2011-12-15 Nec Corporation Method of redistributing functional element
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
US9407997B2 (en) 2010-10-12 2016-08-02 Invensense, Inc. Microphone package with embedded ASIC
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2012256675A (ja) * 2011-06-08 2012-12-27 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びその製造方法
US9093416B2 (en) * 2011-11-28 2015-07-28 Infineon Technologies Ag Chip-package and a method for forming a chip-package
CN103137613B (zh) * 2011-11-29 2017-07-14 华进半导体封装先导技术研发中心有限公司 制备有源芯片封装基板的方法
DE112011105892T5 (de) * 2011-11-29 2014-09-11 Institute of Microelectronics, Chinese Academy of Sciences Verpackungssubstrat für einen aktiven Chip und Verfahren zu dessen Herstellung
CN104576883B (zh) 2013-10-29 2018-11-16 普因特工程有限公司 芯片安装用阵列基板及其制造方法
US9881962B2 (en) * 2013-12-10 2018-01-30 Sony Corporation Semiconductor apparatus, solid state imaging device, imaging apparatus and electronic equipment, and manufacturing method thereof
US9673171B1 (en) 2014-03-26 2017-06-06 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
DE102014118462A1 (de) 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Semiflexible Leiterplatte mit eingebetteter Komponente
DE102014118464A1 (de) 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplatte mit einem asymmetrischen Schichtenaufbau
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
JP6705501B2 (ja) * 2016-05-25 2020-06-03 日立化成株式会社 封止構造体の製造方法
WO2019004264A1 (ja) 2017-06-30 2019-01-03 株式会社村田製作所 電子部品モジュール及びその製造方法

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US5656250A (en) * 1994-06-27 1997-08-12 Jiro Hiraishi, Director-General, Agency Of Industrial Science And Technology Three-dimensional network structure comprising spherical silica particles and method of producing same
US6166433A (en) * 1998-03-26 2000-12-26 Fujitsu Limited Resin molded semiconductor device and method of manufacturing semiconductor package
US6255739B1 (en) * 1998-12-02 2001-07-03 Kabushiki Kaisha Toshiba Semiconductor device
US20040113215A1 (en) * 2002-07-31 2004-06-17 Kyocera Corporation Surface acoustic wave device and method for manufacturing same

Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

Also Published As

Publication number Publication date
KR20060051422A (ko) 2006-05-19
US7312536B2 (en) 2007-12-25
EP1650798A3 (en) 2009-03-11
US20060087045A1 (en) 2006-04-27
TW200614900A (en) 2006-05-01
EP1650798A2 (en) 2006-04-26
CN1819160A (zh) 2006-08-16
JP2006120943A (ja) 2006-05-11

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