CN100423191C - 蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物 - Google Patents

蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物 Download PDF

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Publication number
CN100423191C
CN100423191C CNB038191784A CN03819178A CN100423191C CN 100423191 C CN100423191 C CN 100423191C CN B038191784 A CNB038191784 A CN B038191784A CN 03819178 A CN03819178 A CN 03819178A CN 100423191 C CN100423191 C CN 100423191C
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China
Prior art keywords
plasma
corrosion agent
agent material
etching
photo anti
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Expired - Fee Related
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CNB038191784A
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English (en)
Chinese (zh)
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CN1689142A (zh
Inventor
Y·K·泰勒
W·阮
C·G·N·李
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CNB038191784A 2002-08-14 2003-07-31 蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物 Expired - Fee Related CN100423191C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/219,995 US6923920B2 (en) 2002-08-14 2002-08-14 Method and compositions for hardening photoresist in etching processes
US10/219,995 2002-08-14

Publications (2)

Publication Number Publication Date
CN1689142A CN1689142A (zh) 2005-10-26
CN100423191C true CN100423191C (zh) 2008-10-01

Family

ID=31886605

Family Applications (1)

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CNB038191784A Expired - Fee Related CN100423191C (zh) 2002-08-14 2003-07-31 蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物

Country Status (8)

Country Link
US (2) US6923920B2 (enExample)
EP (1) EP1529308A1 (enExample)
JP (1) JP2005535936A (enExample)
KR (1) KR100990064B1 (enExample)
CN (1) CN100423191C (enExample)
AU (1) AU2003257999A1 (enExample)
TW (1) TWI307121B (enExample)
WO (1) WO2004017390A1 (enExample)

Families Citing this family (20)

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US6962878B2 (en) * 2003-04-17 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce photoresist mask line dimensions
US7005386B1 (en) * 2003-09-05 2006-02-28 Advanced Micro Devices, Inc. Method for reducing resist height erosion in a gate etch process
JP2005109068A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US20050147926A1 (en) * 2004-01-02 2005-07-07 Nanya Technology Corporation Method for processing photoresist
US20060154184A1 (en) * 2005-01-12 2006-07-13 International Business Machines Corporation Method for reducing feature line edge roughness
KR100674967B1 (ko) * 2005-04-06 2007-01-26 삼성전자주식회사 더블 패터닝 방식을 이용한 미세 피치를 갖는 포토레지스트패턴 형성방법
US7390753B2 (en) * 2005-11-14 2008-06-24 Taiwan Semiconductor Mfg. Co., Ltd. In-situ plasma treatment of advanced resists in fine pattern definition
JP5362176B2 (ja) * 2006-06-12 2013-12-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
JP5128421B2 (ja) 2008-09-04 2013-01-23 東京エレクトロン株式会社 プラズマ処理方法およびレジストパターンの改質方法
JP5544914B2 (ja) * 2010-02-15 2014-07-09 大日本印刷株式会社 反射型マスクの製造方法
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
JP5142236B1 (ja) 2011-11-15 2013-02-13 エルシード株式会社 エッチング方法
US9105587B2 (en) * 2012-11-08 2015-08-11 Micron Technology, Inc. Methods of forming semiconductor structures with sulfur dioxide etch chemistries
JP6017928B2 (ja) * 2012-11-09 2016-11-02 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN103021925A (zh) * 2012-12-21 2013-04-03 上海宏力半导体制造有限公司 Sti的制作工艺、沟槽的刻蚀方法和光刻胶的处理方法
KR101989707B1 (ko) * 2014-07-08 2019-06-14 도쿄엘렉트론가부시키가이샤 네거티브톤 현상제 겸용 포토레지스트 조성물 및 이용 방법
JP6736314B2 (ja) * 2015-06-30 2020-08-05 エイブリック株式会社 半導体装置の製造方法
CN107564803B (zh) * 2017-08-31 2020-04-17 京东方科技集团股份有限公司 刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法
KR102841479B1 (ko) 2021-05-10 2025-07-31 삼성전자주식회사 반도체 장치의 제조 방법

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09270420A (ja) * 1996-03-29 1997-10-14 Nippon Steel Corp 半導体装置の製造方法
JPH10261627A (ja) * 1997-03-19 1998-09-29 Oki Electric Ind Co Ltd 半導体装置の製造方法
US5843835A (en) * 1996-04-01 1998-12-01 Winbond Electronics Corporation Damage free gate dielectric process during gate electrode plasma etching
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
US6103632A (en) * 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US6121154A (en) * 1997-12-23 2000-09-19 Lam Research Corporation Techniques for etching with a photoresist mask
JP2001237218A (ja) * 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法
US6299788B1 (en) * 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
US20010050413A1 (en) * 1999-04-15 2001-12-13 Li Li Method of controlling striations and CD loss in contact oxide etch

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US5749389A (en) * 1993-12-22 1998-05-12 Liquid Air Corporation Purgeable connection for gas supply cabinet
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
KR100447263B1 (ko) * 1999-12-30 2004-09-07 주식회사 하이닉스반도체 식각 폴리머를 이용한 반도체 소자의 제조방법
EP1223607A4 (en) * 2000-05-25 2003-03-12 Toppan Printing Co Ltd SUBSTRATE FOR TRANSFER MASK, TRANSFER MASK AND MANUFACTURING METHOD THEREOF
US6630288B2 (en) * 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6673498B1 (en) * 2001-11-02 2004-01-06 Lsi Logic Corporation Method for reticle formation utilizing metal vaporization

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
JPH09270420A (ja) * 1996-03-29 1997-10-14 Nippon Steel Corp 半導体装置の製造方法
US5843835A (en) * 1996-04-01 1998-12-01 Winbond Electronics Corporation Damage free gate dielectric process during gate electrode plasma etching
JPH10261627A (ja) * 1997-03-19 1998-09-29 Oki Electric Ind Co Ltd 半導体装置の製造方法
US6103632A (en) * 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US6121154A (en) * 1997-12-23 2000-09-19 Lam Research Corporation Techniques for etching with a photoresist mask
US6299788B1 (en) * 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
US20010050413A1 (en) * 1999-04-15 2001-12-13 Li Li Method of controlling striations and CD loss in contact oxide etch
JP2001237218A (ja) * 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US20050230352A1 (en) 2005-10-20
US20040079727A1 (en) 2004-04-29
KR20050047091A (ko) 2005-05-19
AU2003257999A1 (en) 2004-03-03
JP2005535936A (ja) 2005-11-24
US6923920B2 (en) 2005-08-02
TW200407998A (en) 2004-05-16
CN1689142A (zh) 2005-10-26
EP1529308A1 (en) 2005-05-11
WO2004017390A1 (en) 2004-02-26
KR100990064B1 (ko) 2010-10-26
TWI307121B (en) 2009-03-01

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