KR100990064B1 - 식각 공정에서 포토레지스트를 경화하는 방법 및 조성물 - Google Patents

식각 공정에서 포토레지스트를 경화하는 방법 및 조성물 Download PDF

Info

Publication number
KR100990064B1
KR100990064B1 KR1020057002028A KR20057002028A KR100990064B1 KR 100990064 B1 KR100990064 B1 KR 100990064B1 KR 1020057002028 A KR1020057002028 A KR 1020057002028A KR 20057002028 A KR20057002028 A KR 20057002028A KR 100990064 B1 KR100990064 B1 KR 100990064B1
Authority
KR
South Korea
Prior art keywords
photoresist material
plasma
wafer
curing
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020057002028A
Other languages
English (en)
Korean (ko)
Other versions
KR20050047091A (ko
Inventor
유선 김 테일러
웬디 뉴옌
크리스 지. 엔. 리
Original Assignee
램 리써치 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 램 리써치 코포레이션 filed Critical 램 리써치 코포레이션
Publication of KR20050047091A publication Critical patent/KR20050047091A/ko
Application granted granted Critical
Publication of KR100990064B1 publication Critical patent/KR100990064B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020057002028A 2002-08-14 2003-07-31 식각 공정에서 포토레지스트를 경화하는 방법 및 조성물 Expired - Fee Related KR100990064B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/219,995 US6923920B2 (en) 2002-08-14 2002-08-14 Method and compositions for hardening photoresist in etching processes
US10/219,995 2002-08-14

Publications (2)

Publication Number Publication Date
KR20050047091A KR20050047091A (ko) 2005-05-19
KR100990064B1 true KR100990064B1 (ko) 2010-10-26

Family

ID=31886605

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057002028A Expired - Fee Related KR100990064B1 (ko) 2002-08-14 2003-07-31 식각 공정에서 포토레지스트를 경화하는 방법 및 조성물

Country Status (8)

Country Link
US (2) US6923920B2 (enExample)
EP (1) EP1529308A1 (enExample)
JP (1) JP2005535936A (enExample)
KR (1) KR100990064B1 (enExample)
CN (1) CN100423191C (enExample)
AU (1) AU2003257999A1 (enExample)
TW (1) TWI307121B (enExample)
WO (1) WO2004017390A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6962878B2 (en) * 2003-04-17 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce photoresist mask line dimensions
US7005386B1 (en) * 2003-09-05 2006-02-28 Advanced Micro Devices, Inc. Method for reducing resist height erosion in a gate etch process
JP2005109068A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US20050147926A1 (en) * 2004-01-02 2005-07-07 Nanya Technology Corporation Method for processing photoresist
US20060154184A1 (en) * 2005-01-12 2006-07-13 International Business Machines Corporation Method for reducing feature line edge roughness
KR100674967B1 (ko) * 2005-04-06 2007-01-26 삼성전자주식회사 더블 패터닝 방식을 이용한 미세 피치를 갖는 포토레지스트패턴 형성방법
US7390753B2 (en) * 2005-11-14 2008-06-24 Taiwan Semiconductor Mfg. Co., Ltd. In-situ plasma treatment of advanced resists in fine pattern definition
JP5362176B2 (ja) * 2006-06-12 2013-12-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
JP5128421B2 (ja) 2008-09-04 2013-01-23 東京エレクトロン株式会社 プラズマ処理方法およびレジストパターンの改質方法
JP5544914B2 (ja) * 2010-02-15 2014-07-09 大日本印刷株式会社 反射型マスクの製造方法
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
JP5142236B1 (ja) 2011-11-15 2013-02-13 エルシード株式会社 エッチング方法
US9105587B2 (en) * 2012-11-08 2015-08-11 Micron Technology, Inc. Methods of forming semiconductor structures with sulfur dioxide etch chemistries
JP6017928B2 (ja) * 2012-11-09 2016-11-02 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN103021925A (zh) * 2012-12-21 2013-04-03 上海宏力半导体制造有限公司 Sti的制作工艺、沟槽的刻蚀方法和光刻胶的处理方法
KR101989707B1 (ko) * 2014-07-08 2019-06-14 도쿄엘렉트론가부시키가이샤 네거티브톤 현상제 겸용 포토레지스트 조성물 및 이용 방법
JP6736314B2 (ja) * 2015-06-30 2020-08-05 エイブリック株式会社 半導体装置の製造方法
CN107564803B (zh) * 2017-08-31 2020-04-17 京东方科技集团股份有限公司 刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法
KR102841479B1 (ko) 2021-05-10 2025-07-31 삼성전자주식회사 반도체 장치의 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018252A1 (en) * 1999-12-30 2001-08-30 Park Won Soung Method for fabricating semiconductor device by using etching polymer
US20010050413A1 (en) * 1999-04-15 2001-12-13 Li Li Method of controlling striations and CD loss in contact oxide etch

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5749389A (en) * 1993-12-22 1998-05-12 Liquid Air Corporation Purgeable connection for gas supply cabinet
US5976769A (en) 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
JPH09270420A (ja) 1996-03-29 1997-10-14 Nippon Steel Corp 半導体装置の製造方法
US5843835A (en) 1996-04-01 1998-12-01 Winbond Electronics Corporation Damage free gate dielectric process during gate electrode plasma etching
JP3484317B2 (ja) * 1997-03-19 2004-01-06 沖電気工業株式会社 半導体装置の製造方法
US6103632A (en) 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US6121154A (en) 1997-12-23 2000-09-19 Lam Research Corporation Techniques for etching with a photoresist mask
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
US6299788B1 (en) 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
JP2001237218A (ja) 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法
EP1223607A4 (en) * 2000-05-25 2003-03-12 Toppan Printing Co Ltd SUBSTRATE FOR TRANSFER MASK, TRANSFER MASK AND MANUFACTURING METHOD THEREOF
US6630288B2 (en) * 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6673498B1 (en) * 2001-11-02 2004-01-06 Lsi Logic Corporation Method for reticle formation utilizing metal vaporization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010050413A1 (en) * 1999-04-15 2001-12-13 Li Li Method of controlling striations and CD loss in contact oxide etch
US20010018252A1 (en) * 1999-12-30 2001-08-30 Park Won Soung Method for fabricating semiconductor device by using etching polymer

Also Published As

Publication number Publication date
US20050230352A1 (en) 2005-10-20
US20040079727A1 (en) 2004-04-29
KR20050047091A (ko) 2005-05-19
AU2003257999A1 (en) 2004-03-03
JP2005535936A (ja) 2005-11-24
US6923920B2 (en) 2005-08-02
TW200407998A (en) 2004-05-16
CN1689142A (zh) 2005-10-26
EP1529308A1 (en) 2005-05-11
WO2004017390A1 (en) 2004-02-26
TWI307121B (en) 2009-03-01
CN100423191C (zh) 2008-10-01

Similar Documents

Publication Publication Date Title
KR100990064B1 (ko) 식각 공정에서 포토레지스트를 경화하는 방법 및 조성물
KR101476435B1 (ko) 다중-레이어 레지스트 플라즈마 에치 방법
US5007982A (en) Reactive ion etching of silicon with hydrogen bromide
US6716571B2 (en) Selective photoresist hardening to facilitate lateral trimming
US7670759B2 (en) Micro pattern forming method and semiconductor device manufacturing method
CN1333436C (zh) 形成次平版印刷的光阻材料图案的制作方法
JP2009529784A (ja) 集積回路の限界寸法を制御するトリム工程
US6156629A (en) Method for patterning a polysilicon gate in deep submicron technology
JP2001308076A (ja) 半導体装置の製造方法
US20020045331A1 (en) Method of producing a semiconductor device using feature trimming
US20050003310A1 (en) Etching process including plasma pretreatment for generating fluorine-free carbon-containing polymer on a photoresist pattern
JP2005535936A5 (enExample)
US20020003126A1 (en) Method of etching silicon nitride
KR20030062200A (ko) 레지스트 패턴 형성방법
US20030003683A1 (en) Plasma enhanced method for increasing silicon-containing photoresist selectivity
KR100239719B1 (ko) 반도체 소자의 제조를 위한 유기막의 식각 방법
JP3277414B2 (ja) ドライエッチング方法
US7670958B2 (en) Etching methods
TW200414301A (en) Forming bilayer resist patterns
KR100687858B1 (ko) 반도체소자의 패터닝 방법
TWI249202B (en) Dielectric etching method to prevent photoresist damage and bird's beak
CN100444025C (zh) 光刻胶修整方法
KR20010040050A (ko) 실리콘 산화막 및 유기막 에칭 장치 및 방법
JP2004172312A (ja) 半導体装置の製造方法
CN1437073A (zh) 有机底部抗反射涂布层的蚀刻方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20131008

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20141007

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20151007

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20161012

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20171013

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20181021

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20181021