CN100394593C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN100394593C CN100394593C CNB2005100844203A CN200510084420A CN100394593C CN 100394593 C CN100394593 C CN 100394593C CN B2005100844203 A CNB2005100844203 A CN B2005100844203A CN 200510084420 A CN200510084420 A CN 200510084420A CN 100394593 C CN100394593 C CN 100394593C
- Authority
- CN
- China
- Prior art keywords
- wiring layer
- insulating barrier
- lead
- semiconductor device
- wire structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
绝缘膜 | 弹性模量(GPa) | 抗张膜强度(MPa) | 抗张伸展率(%) | 热膨胀系数(ppm/℃) |
A | 0.12 | 10 | 24 | 250 |
B | 0.2 | 14 | 21 | 197 |
C | 0.3 | 29 | 47 | 130 |
D | 0.52 | 42 | 57 | 130 |
E | 1.5 | 85 | 17 | 40 |
F | 2.5 | 122 | 23 | 39 |
G | 2.8 | 148 | 56 | 31 |
H | 3.0 | 130 | 40 | 36 |
I | 3.2 | 140 | 30 | 50 |
J | 4.7 | 226 | 55 | 17 |
K | 7.9 | 220 | 15 | 10 |
Claims (13)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004208375A JP4072523B2 (ja) | 2004-07-15 | 2004-07-15 | 半導体装置 |
JP2004208375 | 2004-07-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1722429A CN1722429A (zh) | 2006-01-18 |
CN100394593C true CN100394593C (zh) | 2008-06-11 |
Family
ID=35598601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100844203A Active CN100394593C (zh) | 2004-07-15 | 2005-07-15 | 半导体器件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7348673B2 (zh) |
JP (1) | JP4072523B2 (zh) |
CN (1) | CN100394593C (zh) |
TW (1) | TWI266396B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
WO2008114609A1 (ja) * | 2007-03-19 | 2008-09-25 | Nec Corporation | 半導体装置及びその製造方法 |
JPWO2008126468A1 (ja) * | 2007-03-30 | 2010-07-22 | 日本電気株式会社 | 半導体装置及び半導体装置の製造方法 |
JP4953132B2 (ja) * | 2007-09-13 | 2012-06-13 | 日本電気株式会社 | 半導体装置 |
JP2009111333A (ja) * | 2007-10-12 | 2009-05-21 | Panasonic Corp | 半導体装置 |
KR100910231B1 (ko) * | 2007-11-30 | 2009-07-31 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 |
JPWO2010026956A1 (ja) * | 2008-09-02 | 2012-02-02 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO2010047227A1 (ja) * | 2008-10-21 | 2010-04-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US8643149B2 (en) * | 2009-03-03 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress barrier structures for semiconductor chips |
JP5559775B2 (ja) * | 2009-04-30 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5552261B2 (ja) * | 2009-05-12 | 2014-07-16 | パナソニック株式会社 | 半導体装置 |
US9024431B2 (en) * | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
JPWO2011089936A1 (ja) * | 2010-01-22 | 2013-05-23 | 日本電気株式会社 | 機能素子内蔵基板及び配線基板 |
JPWO2011108308A1 (ja) * | 2010-03-04 | 2013-06-24 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
JP2011187473A (ja) * | 2010-03-04 | 2011-09-22 | Nec Corp | 半導体素子内蔵配線基板 |
US8710639B2 (en) | 2010-04-08 | 2014-04-29 | Nec Corporation | Semiconductor element-embedded wiring substrate |
JP5590985B2 (ja) * | 2010-06-21 | 2014-09-17 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US9472521B2 (en) | 2012-05-30 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
US9112148B2 (en) | 2013-09-30 | 2015-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell structure with laterally offset BEVA/TEVA |
US9178144B1 (en) | 2014-04-14 | 2015-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell with bottom electrode |
US10186484B2 (en) | 2014-06-16 | 2019-01-22 | Intel Corporation | Metal on both sides with clock gated-power and signal routing underneath |
US9209392B1 (en) | 2014-10-14 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell with bottom electrode |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11219978A (ja) * | 1998-02-02 | 1999-08-10 | Hitachi Chem Co Ltd | 電子部品装置 |
US20020068383A1 (en) * | 1997-10-03 | 2002-06-06 | Nec Corporation | Chip size package semiconductor device and method of forming the same |
JP2003204169A (ja) * | 2002-01-10 | 2003-07-18 | Toppan Printing Co Ltd | 可撓性を有する多層配線板 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4190602B2 (ja) | 1997-08-28 | 2008-12-03 | 株式会社ルネサステクノロジ | 半導体装置 |
JPH11204560A (ja) | 1998-01-09 | 1999-07-30 | Matsushita Electron Corp | 半導体装置及びその製造方法 |
JP3116926B2 (ja) | 1998-11-16 | 2000-12-11 | 日本電気株式会社 | パッケージ構造並びに半導体装置、パッケージ製造方法及び半導体装置製造方法 |
JP2000323628A (ja) | 1999-05-10 | 2000-11-24 | Hitachi Ltd | 半導体装置とその製造方法、およびこれを用いた電子機器 |
JP4040363B2 (ja) | 2002-05-20 | 2008-01-30 | 富士通株式会社 | 半導体装置 |
JP3811473B2 (ja) * | 2003-02-25 | 2006-08-23 | 富士通株式会社 | 半導体装置 |
-
2004
- 2004-07-15 JP JP2004208375A patent/JP4072523B2/ja not_active Expired - Fee Related
-
2005
- 2005-07-12 TW TW094123524A patent/TWI266396B/zh not_active IP Right Cessation
- 2005-07-14 US US11/180,729 patent/US7348673B2/en active Active
- 2005-07-15 CN CNB2005100844203A patent/CN100394593C/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020068383A1 (en) * | 1997-10-03 | 2002-06-06 | Nec Corporation | Chip size package semiconductor device and method of forming the same |
JPH11219978A (ja) * | 1998-02-02 | 1999-08-10 | Hitachi Chem Co Ltd | 電子部品装置 |
JP2003204169A (ja) * | 2002-01-10 | 2003-07-18 | Toppan Printing Co Ltd | 可撓性を有する多層配線板 |
Also Published As
Publication number | Publication date |
---|---|
CN1722429A (zh) | 2006-01-18 |
JP4072523B2 (ja) | 2008-04-09 |
JP2006032600A (ja) | 2006-02-02 |
TW200605289A (en) | 2006-02-01 |
TWI266396B (en) | 2006-11-11 |
US7348673B2 (en) | 2008-03-25 |
US20060012029A1 (en) | 2006-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Co-patentee after: Renesas Electronics Corporation Patentee after: NEC Corp. Address before: Tokyo, Japan Co-patentee before: NEC Corp. Patentee before: NEC Corp. |
|
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER OWNER: NEC CORP. Effective date: 20130712 Free format text: FORMER OWNER: RENESAS ELECTRONICS CORPORATION Effective date: 20130712 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130712 Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Tokyo, Japan Patentee before: NEC Corp. Patentee before: Renesas Electronics Corporation |
|
CP02 | Change in the address of a patent holder | ||
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corporation |