US20010051393A1 - Method of making a semiconductor device having a stress relieving mechanism - Google Patents

Method of making a semiconductor device having a stress relieving mechanism Download PDF

Info

Publication number
US20010051393A1
US20010051393A1 US09/884,378 US88437801A US2001051393A1 US 20010051393 A1 US20010051393 A1 US 20010051393A1 US 88437801 A US88437801 A US 88437801A US 2001051393 A1 US2001051393 A1 US 2001051393A1
Authority
US
United States
Prior art keywords
layer
wiring
semiconductor chip
buffer layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/884,378
Other versions
US6423571B2 (en
Inventor
Masahiko Ogino
Akira Nagai
Shuji Eguchi
Toshiaki Ishii
Masanori Segawa
Haruo Akahoshi
Akio Takahashi
Takao Miwa
Naotaka Tanaka
Ichirou Anjou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/809,233 external-priority patent/US6028364A/en
Application filed by Individual filed Critical Individual
Priority to US09/884,378 priority Critical patent/US6423571B2/en
Publication of US20010051393A1 publication Critical patent/US20010051393A1/en
Application granted granted Critical
Publication of US6423571B2 publication Critical patent/US6423571B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Definitions

  • the present invention relates to a semiconductor device used for high density packaging, multi-chip module, bare chip packaging, and the like, and a packaging structure of the semiconductor device.
  • packages of semiconductor devices are being developed from a pin insertion type to a surface packaging type for increasing the packaging densities, and also developed from a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type for coping with the multi-pin arrangement.
  • DIP Dual Inline Package
  • QFP Quad Flat Package
  • PGA Peripheral Component Interconnect Express
  • the QFP is difficult to cope with the multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package and are also liable to be deformed due to finer diameters thereof.
  • the PGA has a limitation in coping with both high speed processing and surface packaging because it is so configured that terminals to be connected to a packaging substrate are elongated and very collectively arranged.
  • the terminals to be connected to a packaging substrate are formed into ball-like shapes, they can be arranged in a dispersed manner over the entire packaging surface without such deformation of leads as found in the QFP, so that pitches between the terminals become larger, to thereby make surface packaging easy; and also since the lengths of the connection terminals are shorter than those of the PGA, an inductance component becomes smaller and thereby a signal transmission speed becomes faster, with a result that such a package is allowed to cope with high speed processing.
  • an elastic body is inserted as an interposer between a semiconductor chip and terminals of a packaging substrate for relieving a thermal stress produced due to a difference in thermal expansion between the packaging substrate and the semiconductor chip upon packaging thereof.
  • the semiconductor device having such a structure has problems depending on the use of gold wire bonding for connection with upper electrodes of the semiconductor chip; namely, since the connection portions connected to the gold wires are concentrated only at a peripheral portion of the chip, the structure has a spontaneous limitation in coping with the further increasing futuristic demand for multi-pin arrangement and higher processing speed of semiconductor devices and has also an inconvenience in terms of mass-production and improvement in production yield because of the increased number of production steps due to the complexity thereof.
  • Japanese Patent Laid-open No. Hei 5-326625 discloses an improved packaging structure of a flip-chip type package in which a LSI chip having solder bumps is mounted on a multi-layered wiring ceramic substrate having solder bumps, wherein a sealing member is filled between the LSI chip and the multi-layered wiring ceramic substrate as a carrier substrate.
  • the above packaging structure seems to have a problem in terms of higher density interconnection, higher response speed of signals, and miniaturization of the package, because the use of the ceramic substrate as multiple wiring layers makes it difficult to reduce a dielectric constant.
  • Another problem of such a package resides in the production step requiring high temperature burning for ceramic, and in difficult handling of the brittle, thin ceramic substrate.
  • Objects of the present invention are to provide a semiconductor device capable of coping with the further increasing futuristic demand for high speed processing and high density packaging and being high in reliability in connection with a packaging substrate; and to provide a packaging structure of the semiconductor device.
  • a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof, and multiple wiring layers.
  • a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof.
  • a packaging structure connected to and mounted on the packaging substrate via the ball-like terminals disposed in a grid array.
  • the above-described multi-layered wiring structure is required to attain two purposes: to achieve electric connection between the semiconductor device and a packaging substrate when the semiconductor device is mounted on the packaging substrate; and to relieve a thermal stress produced between the semiconductor device and the packaging substrate upon packaging thereof. Accordingly, the features of the present invention reside in that
  • the above multi-layered wiring structure includes two components, that is, multiple wiring layers for transmitting an electric signal and a buffer layer for relieving a thermal stress; or
  • an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between a semiconductor chip and a packaging substrate after packaging thereof, whereby serving as the function of the buffer layer.
  • the above multi-layered wiring structure is preferably composed of three or more layers including a conductive layer portion having a ground layer, power supply layer, and wiring layer. This makes it possible to increase a signal transmission speed and to reduce the occurrence of noise.
  • Each of the buffer layer and the insulating layer is preferably made of a material having a low dielectric constant.
  • FIG. 1 shows a relationship between the dielectric constant and each of the thickness of the insulating layer and the transmission delay time.
  • the delay time Td can be given by substituting a dielectric constant ⁇ r of the insulating layer in the following equation (2).
  • Z o 60 ⁇ r ⁇ ln ⁇ ( 1.9 ⁇ ⁇ h w ⁇ ( 0.8 + t / w ) ) ( 1 )
  • the use of a low dielectric constant material enables thinning of the film thickness h of the insulating layer (that is, thinning of the semiconductor device) and also enables shortening of the delay time (that is, increase in response speed).
  • the insulating layer is made of alumina which is a typical material of a ceramic substrate, since alumina has a dielectric constant of 9.34, the film thickness h of the insulating layer becomes 606 ⁇ m.
  • the insulating layer is made of polyimide having a dielectric constant of 3.0, the film thickness thereof can be reduced to 180 ⁇ m.
  • the delay time Td of the insulating layer made of polyimide it can be shortened by about one-half of that of the insulating layer made of alumina, that is, from 10.2 ns/m to 5.78 ns/m.
  • the above insulating layer is preferably made of a low thermal expansion polyimide having a linear expansion coefficient of 20 ppm/K or less or a silicon elastomer having an elastic modulus of 10 kg/mm 2 or less.
  • a low thermal expansion polyimide having a linear expansion coefficient of 20 ppm/K or less or a silicon elastomer having an elastic modulus of 10 kg/mm 2 or less.
  • Specific examples of the above low thermal expansion polyimide may include a polyimide obtained by polymerization of pyromellitic acid dianhydride and any one of 2,5-diaminotoluene, diaminodurene, benzidine, 3,3′-dimethylbenzidine, 3,3 ′-dimethoxybenzidine, 4,4′-diaminoterphenyl, 1,5-diaminonaphthalene, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3′, 4,4′-benzophenonetetracarboxylic acid dianhydride and any one of 3,3′-dimethylbenzidine, 4,4′-diaminoterphenyl, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3′, 4,4′-biphenyltetracarboxylic acid dianhydride and any one of paraphenylenediamine, 2,5
  • the present inventors have made the analysis of a thermal stress of a semiconductor device upon packaging thereof, and found that an elastic body having an elastic modulus of 10 kg/mm 2 or less enables the relief of the thermal stress of the semiconductor device without any influence of the linear expansion coefficient of the elastic body. Accordingly, the object of the present invention can be attained by the use of an elastic body having an elastic modulus of 10 kg/mm 2 .
  • the elastic modulus of the above elastomer is more than 10 kg/mm 2 , the elastic body is affected by the linear expansion coefficient thereof, thereby reducing the stress reliving effect of the elastomer.
  • the elastic body having an elastic modulus of 10 kg/mm 2 is preferably made of an elastomer or a low elastic engineering plastic.
  • Specific examples of the above elastomer may include fluorine rubber, silicon fluoride rubber, acrylic rubber, hydrogenated nitrilo rubber, ethylene propylene rubber, chlorosulfonated polystyrene rubber, epichlorohydrin rubber, butyl rubber, and urethane rubber.
  • Specific examples of the above low elastic engineering plastic may include polycarbonate (PC)/acrylonitrile butadiene styrene (ABS) alloy, polysiloxanedimethylterephthalate (PCT)/polyethyleneterephthalate (PET), copolymerized polybuthylene terephthalate) (PBT)/polycarbonate (PC) alloy, polytertafluoroethylene (PTFE), florinated ethylene propylene polymer (FET), polyalylate, polyamide (PA)/acrylonitrile butadiene styrene (ABS) alloy, modified epoxy resin, and modified polyolefin resin.
  • PC polycarbonate
  • ABS acrylonitrile butadiene styrene
  • ABS polystyrene
  • PCT polysiloxanedimethylterephthalate
  • PET polyethyleneterephthalate
  • PBT copolymerized polybuthylene terephthalate
  • PC polycarbonate
  • thermosetting resins such as epoxy resin, unsaturated polyester resin, epoxyisocyanate resin, maleimide resin, maleimide epoxy resin, cyanic acid ester resin, cyanic acid ester epoxy resin, cyanic acid ester maleimide resin, phenol resin, diallyl phthalate resin, urethane resin, cyanamide resin, and maleimide cyanamide resin.
  • thermosetting resins such as epoxy resin, unsaturated polyester resin, epoxyisocyanate resin, maleimide resin, maleimide epoxy resin, cyanic acid ester resin, cyanic acid ester epoxy resin, cyanic acid ester maleimide resin, phenol resin, diallyl phthalate resin, urethane resin, cyanamide resin, and maleimide cyanamide resin.
  • thermosetting resin is less in thermal deformation at a high temperature and is excellent in heat resistance.
  • the hardened material thus obtained is desired to have a dielectric strength of 10,000 V/cm or more, and to have a heat resistance withstanding a temperature of 150° C. or more for a long period of time.
  • the above high molecular material before being hardened is preferably adjustable in its viscosity by a solvent, and more preferably, it exhibits such a photosensitive property as to be hardened by light emission or the like.
  • the multiple wiring layers of the present invention can be typically realized in accordance with either of two processes shown in FIGS. 2 and 3.
  • the semiconductor of the present invention can be fabricated in accordance with the following steps: first, forming a wiring layer by (a) forming an elastomer insulating layer 2 on a semiconductor chip 1 , (b) forming windows 3 for interlayer connection in the insulating layer 2 , and (c) forming a wiring layer by performing interlayer connection 4 ; secondarily, repeating the above steps by the number required for forming necessary layers, to form multiple wiring layers; and finally, (d) forming solder balls 5 as connection terminals to a packaging substrate on the multiple wiring layers.
  • the semiconductor device of the present invention can be fabricated by the following steps: (e) sticking wiring sheet-like pieces 6 to each other, (f) forming windows 3 for interlayer connection in the laminated sheet-like pieces 6 , (g) performing interlayer connection 4 , to form a multi-layered wiring sheet, (h) adhesively bonding the multi-layered wiring sheet on a semiconductor chip via a multi-sword shaped conductor containing buffer layer 7 , to form a multi-layered wiring structure, and finally forming solder bumps on the multi-layered wiring structure.
  • the above multi-sword shaped conductor containing buffer layer is prepared, for example, by piecing a polyimide film (thickness: about 50 ⁇ m) adhesively bonded with a copper foil (thickness: about 18 ⁇ m) at specified positions by excimer laser (KrF: 248 nm, pulse energy: 40 mj/pulse, repeated frequency: 600 Hz at maximum; average output: 24 W), to form holes (diameter: 25 ⁇ m, hole pitch: 40 ⁇ m); burying the holes with a conductive material by plating such as a known chemical copper plating, followed by etching back of the copper foil; applying nonelectrolytic tin plating on both ends of the conductive material buried in the holes, or by casting (for example, potting) an elastomer into a vessel in which a large number of gold wires are erected at specified positions; and adjusting the thickness of the elastomer containing the gold wires after hardening.
  • the multi-sword shaped conductor containing buffer layer can be formed of an anisotropic conductive film which has electric conduction only in the vertical direction.
  • a semiconductor chip is superposed on one side surface of the film. At this time, with respect to the film, only portions connected to electrode portions of the semiconductor chip are made electrically conductive.
  • a multi-layered wiring structure having electrodes corresponding to the electrode portions of the semiconductor chip is superposed on the other side surface of the film. At this time, with respect to the film, only portions connected to the electrodes of the multi-layered wiring structure are made electrically conductive.
  • the multi-sword shaped conductor containing buffer layer is connected to a semiconductor chip by Au/Sn bonding, Sn/Pb bonding, or the like. More specifically, gold is vapor-deposited at electrode portions, to be bonded to each other, of both the chip and buffer layer, followed by forming tin solders thereat by nonelectrolytic tin plating, and in such a state, both the chip and buffer layer are pressed to each other and heated (240-250° C.) for several seconds (2-3 sec), to be thus bonded to each other by melting of the tin solders formed on the electrode portions.
  • the connection of the buffer layer to the multi-layered wiring structure can be performed in the same manner as described above.
  • the ball-like terminals disposed in a grid array on the connection surface of the multi-layered wiring structure to a packaging substrate may be formed of a solder alloy containing tin, zinc or lead; silver; copper or gold into ball-shapes.
  • a ball made of the above metal may be covered with gold.
  • the ball-like terminal may be formed of an alloy of one kind or two or more kinds selected from molybdenum, nickel, copper, platinum and titanium; or may be formed of multi-layered films having layers made of two or more kinds selected from the above metals.
  • the above semiconductor chip may include a linear IC, LSI, logic, memory, gate array, or the like having circuits formed on a semiconductor substrate.
  • the semiconductor device is provided with a heat spreader for assisting heat radiation produced upon operation of the semiconductor chip.
  • the heat spreader is formed of a material excellent in thermal conductivity, for example, a metal having a high thermal conductivity, such as copper.
  • the heat spreader is preferably configured to have a structure (see FIG. 7) in which the semiconductor chip 1 is buried and mounted.
  • a multi-layered wiring structure having an area larger than that of a semiconductor chip can be formed on the heat spreader.
  • the heat spreader having this structure may include heat radiation fins provided on the portions other than the chip mounting surface for increasing the entire heat radiation surface area.
  • the semiconductor device of the present invention may be so configured that two or more of semiconductor chips are mounted on the single multi-layered wiring structure
  • the semiconductor device of the present invention it is possible to dispose ball-like terminals to be connected to a packaging substrate over the entire packaging surface of the multi-layered wiring structure and to eliminate the necessity of gold wire bonding.
  • the semiconductor device of the present invention is allowed to easily cope with multi-pin arrangement, and therefore, it is suitable to higher density and higher integration.
  • the wiring distance can be shortened as compared with the conventional semiconductor device in which the semiconductor chip and the multi-layered wiring structure are soldered to each other by electrode bumps, with a result that an inductance component can be reduced and thereby a signal transmission speed becomes faster, leading to the increased processing speed of the semiconductor device.
  • the use of a low dielectric constant material allows the package to be thinned more than that of the conventional package using the multi-layered ceramic substrate when compared at the same signal frequency
  • the formation of the multi-layered wiring structure having a low elastic modulus on the semiconductor chip makes it possible to reduce a thermal stress produced between a packaging substrate and the semiconductor chip, and hence to improve the reliability in connection of the semiconductor chip to the packaging substrate after packaging thereof.
  • FIG. 1 is a graph showing a relationship between a dielectric constant, and each of the thickness of an insulating film and a transmission delay time;
  • FIG. 2 is a typical view illustrating fabrication steps for realizing the present invention by a sequentially laminating process
  • FIG. 3 is a typical view illustrating fabrication steps for realizing the present invention by a film laminating process
  • FIG. 4 is a typical sectional view of a semiconductor device according to a first example
  • FIG. 5 is a typical sectional view of a semiconductor device according to a second example
  • FIG. 6 is a typical sectional view of a semiconductor device according to a third example.
  • FIG. 7 is a typical sectional view of a semiconductor device according to a fourth example.
  • FIG. 8 is a typical sectional view of a semiconductor device according to a fifth example.
  • FIG. 9 is a typical sectional view of a semiconductor device according to a sixth example.
  • FIG. 4 is a typical sectional view of a semiconductor device according to one example of the present invention.
  • a semiconductor device of the present invention was fabricated in the following procedure using a silicon semiconductor chip 1 having elements such as a transistor, diode, resistor, and the like incorporated on a semiconductor substrate.
  • a first conductive layer 8 made of aluminum was formed on the above-described semiconductor chip 1 in accordance with a specified wiring pattern by a known photoetching process.
  • the substrate was spin-coated with a varnish of polyimide precursor (PIQ, produced by Hitachi Chemical Co., Ltd.) at a rotational speed of from 1,000 to 5,000 rpm, followed by heating in a nitrogen atmosphere at 100° C. for one hour and at 350° C. for 30 minutes to harden the vanish, to thereby form a first insulating film 9 formed of a polyimide film.
  • PIQ polyimide precursor
  • the polyimide film was then spin-coated with a negative type liquid resist (OMR-83, produced by TOKYO OHKA KOGYO CO., LTD), followed by hardening at 90° C. for 30 minutes.
  • OMR-83 negative type liquid resist
  • the resist film thus hardened was then subjected to photoresist patterning, followed by development, and was hardened again in a nitrogen atmosphere at 150° C. for 30 minutes, to thereby form windows in the resist film.
  • the substrate in such a state was immersed in a mixed solution of hydrazine hydrate and ethylene diamine, to form in the polyimide film windows 3 for interlayer connection, and then the photoresist was separated from the polyimide film by a separating agent composed of an alkali solution (N303C, produced by TOKYO OHKA KOGYO CO., LTD).
  • a separating agent composed of an alkali solution N303C, produced by TOKYO OHKA KOGYO CO., LTD.
  • a second conductive layer 10 was formed of Al by vapor-deposition, followed by patterning by the known photoetching process. At this time, the second conductive layer 10 was electrically connected to the first conductive layer 8 through the windows 3 opened at specified positions for interlayer connection.
  • Solder balls 5 made of Sn/Pb (63/37) to be electrically connected to a package substrate were formed in a grid array over the packaging surface of the multiple wiring layers, to form a semiconductor device.
  • FIG. 5 is a typical sectional view of a semiconductor device according to one example of the present invention, wherein multiple wiring layers 14 and a buffer layer 7 are formed as a multi-layered wiring structure.
  • a copper thin film was formed by sputtering on the surface of a silicon semiconductor chip 1 having multiple wiring layers formed with a circuit and windows for electric connection.
  • the copper thin film was etched by a specified process to form a wiring.
  • the copper thin film was then stuck with an adhesive sheet formed of a low thermal expansive polyimide film (X952, produced by Hitachi Chemical, Co., Ltd.) applied with an adhesive, followed by hardening the adhesive, and the adhesive sheet was pierced by laser to form specified holes. Via-stads were formed in the specified holes by nonelectrolytic copper plating, and then a copper film was formed on the adhesive film having the holes by sputtering.
  • a low thermal expansive polyimide film X952, produced by Hitachi Chemical, Co., Ltd.
  • a buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi sword-shaped conductor containing buffer layer 7 was adhesively bonded via solder on the packaging surface of the multiple wiring layers by pressing and heating, and terminals composed of solder balls 5 made of Sn/Pb (63/37) were connected and formed on the packaging surface of the buffer layer 7 , to thereby obtain a semiconductor device.
  • a semiconductor device including two semiconductor chips 1 mounted on the multiple wiring layers 14 was similarly fabricated, which gave the excellent characteristics comparable to those of the semiconductor device having the single semiconductor chip 1 .
  • FIG. 6 is a typical sectional view of a semiconductor device according to one example of the present invention, wherein multiple wiring layers 14 are connected to a circuit formation surface of a silicon semiconductor chip 1 via a multi-sword shaped conductor containing buffer layer 7 .
  • a both side copper-clad laminate (MCLE67, produced by Hitachi Chemical Co., Ltd.) was patterned by etching, and was coated with a permanent resist (Provia 52, produced by Ciba-Geigy Japan Limited), followed by drying, exposure, and development to form photo-via holes, and then the permanent resist was hardened by heating.
  • the laminate was pieced by drilling to form through-holes, followed by nonelectrolytic copper plating to form a copper layer thereon, and then the copper layer was patterned by etching, to thereby form multiple wiring layers 14 .
  • Solder balls 5 were connected in a grid array onto the packaging surface of the multiple wiring layers 14 , and a buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi-sword shaped conductor containing buffer layer 7 was laminated and bonded onto the opposed surface of the multiple wiring layers 14 , to thereby obtain a semiconductor device.
  • the semiconductor device was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • FIG. 7 is a typical sectional view of a semiconductor device according to one example of the present invention.
  • a semiconductor chip 1 was buried in a copper made heat spreader 15 having heat radiation fins and fixed thereto by means of a silicon base adhesive, with the circuit formation surface of the semiconductor chip 1 directed on the packaging side, and a buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi-sword shaped conductor containing buffer layer 7 was similarly buried in the heat spreader 15 and bonded with the circuit formation surface of the semiconductor chip 1 .
  • Multiple wiring layers 15 were formed on the packaging surface of the heat spreader 15 in the following manner.
  • Solder balls 5 were connected in a grid array onto the packaging surface of the multi-layered wiring substrate 14 , to thereby obtain a semiconductor device.
  • the semiconductor device thus obtained was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • the semiconductor device 16 fabricated in the same manner as that in Example 1 was sealed by a transfer molding process using an epoxy resin base mold resin (RM192, produced by Hitachi Chemical Co., Ltd.) as shown in FIG. 8, to obtain a semiconductor device in this example.
  • the transfer molding condition was as follows:
  • mold temperature 180° C.
  • a conventional BGA (Ball Grid Array) type semiconductor device (number of pins: 225, size: 27 mm ⁇ 27 mm) was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • a conventional QFP (Quad Flat Package) type semiconductor device (number of pins: 208, size: 31 mm ⁇ 31 mm) was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • the semiconductor device of the present invention shown in each example does not produce any connection failure in the temperature cycle testing, and is low in inductance, switching noise, and crosstalk per unit length.

Abstract

A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed. The distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in improved connection reliability, and the number of terminals per unit can be increased, because of elimination of wire bonding. The buffer layer can be made of an elastomer, and can have a modulus of elasticity of 10 kg/mm2 or less.

Description

  • This application is a Divisional application of application Ser. No. 09/482,891, filed Jan. 14, 200, which is a Divisional application of application Ser. No. 08/809,233, filed March 1997, which is an application filed under 35 USC 371 of International application Ser. No. PCT/JP95/00714, filed Apr. 12, 1995.[0001]
  • TECHNICAL FIELD
  • The present invention relates to a semiconductor device used for high density packaging, multi-chip module, bare chip packaging, and the like, and a packaging structure of the semiconductor device. [0002]
  • BACKGROUND ART
  • In recent years, the reduced sizes and increased performances of the electronic devices will generate the demand for higher integration, higher density, and higher processing speed of semiconductor devices used for the electronic devices. To meet such a demand, packages of semiconductor devices are being developed from a pin insertion type to a surface packaging type for increasing the packaging densities, and also developed from a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type for coping with the multi-pin arrangement. [0003]
  • Of the packages thus developed, the QFP is difficult to cope with the multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package and are also liable to be deformed due to finer diameters thereof. Besides, the PGA has a limitation in coping with both high speed processing and surface packaging because it is so configured that terminals to be connected to a packaging substrate are elongated and very collectively arranged. [0004]
  • Recently, to solve these problems and to realize a semiconductor device capable of coping with high speed processing, a BGA (Ball Grid Array) package is disclosed in U.S. Pat. No. 5,148,265, which has ball-like connection terminals over the entire packaging surface of a carrier substrate electrically connected to a semiconductor chip by gold wire bonding. In this package, since the terminals to be connected to a packaging substrate are formed into ball-like shapes, they can be arranged in a dispersed manner over the entire packaging surface without such deformation of leads as found in the QFP, so that pitches between the terminals become larger, to thereby make surface packaging easy; and also since the lengths of the connection terminals are shorter than those of the PGA, an inductance component becomes smaller and thereby a signal transmission speed becomes faster, with a result that such a package is allowed to cope with high speed processing. [0005]
  • In the above-described BGA package, an elastic body is inserted as an interposer between a semiconductor chip and terminals of a packaging substrate for relieving a thermal stress produced due to a difference in thermal expansion between the packaging substrate and the semiconductor chip upon packaging thereof. The semiconductor device having such a structure, however, has problems depending on the use of gold wire bonding for connection with upper electrodes of the semiconductor chip; namely, since the connection portions connected to the gold wires are concentrated only at a peripheral portion of the chip, the structure has a spontaneous limitation in coping with the further increasing futuristic demand for multi-pin arrangement and higher processing speed of semiconductor devices and has also an inconvenience in terms of mass-production and improvement in production yield because of the increased number of production steps due to the complexity thereof. [0006]
  • Japanese Patent Laid-open No. Hei 5-326625 discloses an improved packaging structure of a flip-chip type package in which a LSI chip having solder bumps is mounted on a multi-layered wiring ceramic substrate having solder bumps, wherein a sealing member is filled between the LSI chip and the multi-layered wiring ceramic substrate as a carrier substrate. The above packaging structure, however, seems to have a problem in terms of higher density interconnection, higher response speed of signals, and miniaturization of the package, because the use of the ceramic substrate as multiple wiring layers makes it difficult to reduce a dielectric constant. Another problem of such a package resides in the production step requiring high temperature burning for ceramic, and in difficult handling of the brittle, thin ceramic substrate. [0007]
  • Objects of the present invention are to provide a semiconductor device capable of coping with the further increasing futuristic demand for high speed processing and high density packaging and being high in reliability in connection with a packaging substrate; and to provide a packaging structure of the semiconductor device. [0008]
  • DISCLOSURE OF THE INVENTION
  • The gist of the present invention made for solving the above-described problems is as follows: [0009]
  • (1) According to the present invention, there is provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof, and multiple wiring layers. [0010]
  • (2) According to the present invention, there is also provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof. [0011]
  • (3) According to the present invention, there is also provided a packaging structure connected to and mounted on the packaging substrate via the ball-like terminals disposed in a grid array. [0012]
  • The above-described multi-layered wiring structure is required to attain two purposes: to achieve electric connection between the semiconductor device and a packaging substrate when the semiconductor device is mounted on the packaging substrate; and to relieve a thermal stress produced between the semiconductor device and the packaging substrate upon packaging thereof. Accordingly, the features of the present invention reside in that [0013]
  • {circle over (1)} the above multi-layered wiring structure includes two components, that is, multiple wiring layers for transmitting an electric signal and a buffer layer for relieving a thermal stress; or [0014]
  • {circle over (2)} an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between a semiconductor chip and a packaging substrate after packaging thereof, whereby serving as the function of the buffer layer. [0015]
  • The above multi-layered wiring structure is preferably composed of three or more layers including a conductive layer portion having a ground layer, power supply layer, and wiring layer. This makes it possible to increase a signal transmission speed and to reduce the occurrence of noise. [0016]
  • Each of the buffer layer and the insulating layer is preferably made of a material having a low dielectric constant. FIG. 1 shows a relationship between the dielectric constant and each of the thickness of the insulating layer and the transmission delay time. In addition, the film thickness h of the insulating layer is given by the following equation [1]. For example, for the wiring having a width w=50 μm and a height t=30 μm, the film thickness h at a characteristic impedance Z[0017] 0=55 Ω can be calculated by substituting these values in the equation [1].
  • The delay time Td can be given by substituting a dielectric constant ε[0018] r of the insulating layer in the following equation (2). Z o = 60 ɛ r ln ( 1.9 h w ( 0.8 + t / w ) ) ( 1 )
    Figure US20010051393A1-20011213-M00001
  • Td=3.34 {square root}{square root over (εr)}  [2]
  • From the result shown in FIG. 1, it becomes apparent that the use of a low dielectric constant material enables thinning of the film thickness h of the insulating layer (that is, thinning of the semiconductor device) and also enables shortening of the delay time (that is, increase in response speed). For example, in the case where the insulating layer is made of alumina which is a typical material of a ceramic substrate, since alumina has a dielectric constant of 9.34, the film thickness h of the insulating layer becomes 606 μm. On the contrary, in the case where the insulating layer is made of polyimide having a dielectric constant of 3.0, the film thickness thereof can be reduced to 180 μm. With respect to the delay time Td of the insulating layer made of polyimide, it can be shortened by about one-half of that of the insulating layer made of alumina, that is, from 10.2 ns/m to 5.78 ns/m. [0019]
  • The above insulating layer is preferably made of a low thermal expansion polyimide having a linear expansion coefficient of 20 ppm/K or less or a silicon elastomer having an elastic modulus of 10 kg/mm[0020] 2 or less. The use of these materials enables high speed transmission of an electric signal, thinning of the package, and reduction in stress of the package.
  • Specific examples of the above low thermal expansion polyimide may include a polyimide obtained by polymerization of pyromellitic acid dianhydride and any one of 2,5-diaminotoluene, diaminodurene, benzidine, 3,3′-dimethylbenzidine, 3,3 ′-dimethoxybenzidine, 4,4′-diaminoterphenyl, 1,5-diaminonaphthalene, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3′, 4,4′-benzophenonetetracarboxylic acid dianhydride and any one of 3,3′-dimethylbenzidine, 4,4′-diaminoterphenyl, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3′, 4,4′-biphenyltetracarboxylic acid dianhydride and any one of paraphenylenediamine, 2,5-diaminotoluene, benzidine, 3,3′-dimethylbenzidine, 4,4′-diaminoterphenyl, 1,5-diaminonaphthalene, 2,7-diaminofluorene, and 2,5-diaminopyridine. [0021]
  • The present inventors have made the analysis of a thermal stress of a semiconductor device upon packaging thereof, and found that an elastic body having an elastic modulus of 10 kg/mm[0022] 2 or less enables the relief of the thermal stress of the semiconductor device without any influence of the linear expansion coefficient of the elastic body. Accordingly, the object of the present invention can be attained by the use of an elastic body having an elastic modulus of 10 kg/mm2. When the elastic modulus of the above elastomer is more than 10 kg/mm2, the elastic body is affected by the linear expansion coefficient thereof, thereby reducing the stress reliving effect of the elastomer.
  • The elastic body having an elastic modulus of 10 kg/mm[0023] 2 is preferably made of an elastomer or a low elastic engineering plastic.
  • Specific examples of the above elastomer may include fluorine rubber, silicon fluoride rubber, acrylic rubber, hydrogenated nitrilo rubber, ethylene propylene rubber, chlorosulfonated polystyrene rubber, epichlorohydrin rubber, butyl rubber, and urethane rubber. [0024]
  • Specific examples of the above low elastic engineering plastic may include polycarbonate (PC)/acrylonitrile butadiene styrene (ABS) alloy, polysiloxanedimethylterephthalate (PCT)/polyethyleneterephthalate (PET), copolymerized polybuthylene terephthalate) (PBT)/polycarbonate (PC) alloy, polytertafluoroethylene (PTFE), florinated ethylene propylene polymer (FET), polyalylate, polyamide (PA)/acrylonitrile butadiene styrene (ABS) alloy, modified epoxy resin, and modified polyolefin resin. [0025]
  • Other than the above plastics, there may be used a high molecular material selected from one or two or more kinds of thermosetting resins such as epoxy resin, unsaturated polyester resin, epoxyisocyanate resin, maleimide resin, maleimide epoxy resin, cyanic acid ester resin, cyanic acid ester epoxy resin, cyanic acid ester maleimide resin, phenol resin, diallyl phthalate resin, urethane resin, cyanamide resin, and maleimide cyanamide resin. Of these high molecular materials, to attain the object of the present invention, there may be preferably used those having such stable hardening characteristics as not to be hardened at room temperature but to be hardened by heating at a temperature of from 150 to 350° C. for a period of from several minutes to several hours. Such a thermosetting resin is less in thermal deformation at a high temperature and is excellent in heat resistance. [0026]
  • The hardened material thus obtained is desired to have a dielectric strength of 10,000 V/cm or more, and to have a heat resistance withstanding a temperature of 150° C. or more for a long period of time. [0027]
  • The above high molecular material before being hardened is preferably adjustable in its viscosity by a solvent, and more preferably, it exhibits such a photosensitive property as to be hardened by light emission or the like. [0028]
  • The multiple wiring layers of the present invention can be typically realized in accordance with either of two processes shown in FIGS. 2 and 3. [0029]
  • In the sequentially laminating process shown in FIG. 2, the semiconductor of the present invention can be fabricated in accordance with the following steps: first, forming a wiring layer by (a) forming an [0030] elastomer insulating layer 2 on a semiconductor chip 1, (b) forming windows 3 for interlayer connection in the insulating layer 2, and (c) forming a wiring layer by performing interlayer connection 4; secondarily, repeating the above steps by the number required for forming necessary layers, to form multiple wiring layers; and finally, (d) forming solder balls 5 as connection terminals to a packaging substrate on the multiple wiring layers.
  • In the film lamination process shown in FIG. 3, the semiconductor device of the present invention can be fabricated by the following steps: (e) sticking wiring sheet-[0031] like pieces 6 to each other, (f) forming windows 3 for interlayer connection in the laminated sheet-like pieces 6, (g) performing interlayer connection 4, to form a multi-layered wiring sheet, (h) adhesively bonding the multi-layered wiring sheet on a semiconductor chip via a multi-sword shaped conductor containing buffer layer 7, to form a multi-layered wiring structure, and finally forming solder bumps on the multi-layered wiring structure.
  • The above multi-sword shaped conductor containing buffer layer is prepared, for example, by piecing a polyimide film (thickness: about 50 μm) adhesively bonded with a copper foil (thickness: about 18 μm) at specified positions by excimer laser (KrF: 248 nm, pulse energy: 40 mj/pulse, repeated frequency: 600 Hz at maximum; average output: 24 W), to form holes (diameter: 25 μm, hole pitch: 40 μm); burying the holes with a conductive material by plating such as a known chemical copper plating, followed by etching back of the copper foil; applying nonelectrolytic tin plating on both ends of the conductive material buried in the holes, or by casting (for example, potting) an elastomer into a vessel in which a large number of gold wires are erected at specified positions; and adjusting the thickness of the elastomer containing the gold wires after hardening. [0032]
  • The multi-sword shaped conductor containing buffer layer can be formed of an anisotropic conductive film which has electric conduction only in the vertical direction. A semiconductor chip is superposed on one side surface of the film. At this time, with respect to the film, only portions connected to electrode portions of the semiconductor chip are made electrically conductive. On the other hand, a multi-layered wiring structure having electrodes corresponding to the electrode portions of the semiconductor chip is superposed on the other side surface of the film. At this time, with respect to the film, only portions connected to the electrodes of the multi-layered wiring structure are made electrically conductive. [0033]
  • The multi-sword shaped conductor containing buffer layer is connected to a semiconductor chip by Au/Sn bonding, Sn/Pb bonding, or the like. More specifically, gold is vapor-deposited at electrode portions, to be bonded to each other, of both the chip and buffer layer, followed by forming tin solders thereat by nonelectrolytic tin plating, and in such a state, both the chip and buffer layer are pressed to each other and heated (240-250° C.) for several seconds (2-3 sec), to be thus bonded to each other by melting of the tin solders formed on the electrode portions. The connection of the buffer layer to the multi-layered wiring structure can be performed in the same manner as described above. [0034]
  • The ball-like terminals disposed in a grid array on the connection surface of the multi-layered wiring structure to a packaging substrate may be formed of a solder alloy containing tin, zinc or lead; silver; copper or gold into ball-shapes. In this case, such a ball made of the above metal may be covered with gold. By the use of such ball-like terminals, the semiconductor device can be electrically connected to a packaging substrate by melting of the ball-like terminals or by contact or vibration of the ball-like terminals without heating. Other than the above metals, the ball-like terminal may be formed of an alloy of one kind or two or more kinds selected from molybdenum, nickel, copper, platinum and titanium; or may be formed of multi-layered films having layers made of two or more kinds selected from the above metals. [0035]
  • The above semiconductor chip may include a linear IC, LSI, logic, memory, gate array, or the like having circuits formed on a semiconductor substrate. [0036]
  • In the present invention, the semiconductor device is provided with a heat spreader for assisting heat radiation produced upon operation of the semiconductor chip. The heat spreader is formed of a material excellent in thermal conductivity, for example, a metal having a high thermal conductivity, such as copper. In particular, the heat spreader is preferably configured to have a structure (see FIG. 7) in which the [0037] semiconductor chip 1 is buried and mounted. In the heat spreader having such a structure, a multi-layered wiring structure having an area larger than that of a semiconductor chip can be formed on the heat spreader. The heat spreader having this structure may include heat radiation fins provided on the portions other than the chip mounting surface for increasing the entire heat radiation surface area.
  • The semiconductor device of the present invention may be so configured that two or more of semiconductor chips are mounted on the single multi-layered wiring structure [0038]
  • According to the semiconductor device of the present invention, it is possible to dispose ball-like terminals to be connected to a packaging substrate over the entire packaging surface of the multi-layered wiring structure and to eliminate the necessity of gold wire bonding. As a result, when compared with the conventional semiconductor device, the semiconductor device of the present invention is allowed to easily cope with multi-pin arrangement, and therefore, it is suitable to higher density and higher integration. [0039]
  • In the semiconductor device of the present invention, since a distance between the ground layer and the power supply layer in the semiconductor substrate can be shortened and also the semiconductor chip can be directly connected to the multi-layered wiring structure without formation of solder bumps, the wiring distance can be shortened as compared with the conventional semiconductor device in which the semiconductor chip and the multi-layered wiring structure are soldered to each other by electrode bumps, with a result that an inductance component can be reduced and thereby a signal transmission speed becomes faster, leading to the increased processing speed of the semiconductor device. Also, in the present invention, the use of a low dielectric constant material (polyimide, elastomer, or the like) allows the package to be thinned more than that of the conventional package using the multi-layered ceramic substrate when compared at the same signal frequency [0040]
  • Additionally, in the present invention, the formation of the multi-layered wiring structure having a low elastic modulus on the semiconductor chip makes it possible to reduce a thermal stress produced between a packaging substrate and the semiconductor chip, and hence to improve the reliability in connection of the semiconductor chip to the packaging substrate after packaging thereof.[0041]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a graph showing a relationship between a dielectric constant, and each of the thickness of an insulating film and a transmission delay time; [0042]
  • FIG. 2 is a typical view illustrating fabrication steps for realizing the present invention by a sequentially laminating process; [0043]
  • FIG. 3 is a typical view illustrating fabrication steps for realizing the present invention by a film laminating process; [0044]
  • FIG. 4 is a typical sectional view of a semiconductor device according to a first example; [0045]
  • FIG. 5 is a typical sectional view of a semiconductor device according to a second example; [0046]
  • FIG. 6 is a typical sectional view of a semiconductor device according to a third example; [0047]
  • FIG. 7 is a typical sectional view of a semiconductor device according to a fourth example; [0048]
  • FIG. 8 is a typical sectional view of a semiconductor device according to a fifth example; and [0049]
  • FIG. 9 is a typical sectional view of a semiconductor device according to a sixth example.[0050]
  • BEST MODE FOR CARRYING OUT THE INVENTION
  • Hereinafter, the present invention will be described in detail with reference to examples. [0051]
  • EXAMPLE 1
  • FIG. 4 is a typical sectional view of a semiconductor device according to one example of the present invention. A semiconductor device of the present invention was fabricated in the following procedure using a [0052] silicon semiconductor chip 1 having elements such as a transistor, diode, resistor, and the like incorporated on a semiconductor substrate.
  • The upper surface of the [0053] semiconductor chip 1 having a single crystal silicon wafer, a silicon layer formed on the silicon wafer by epitaxial growth, and a circuit formed in the epitaxial growth layer, was covered with a protective layer (not shown) formed of a silicon dioxide film, the protective layer being provided with windows for electric connection.
  • Next, a first [0054] conductive layer 8 made of aluminum was formed on the above-described semiconductor chip 1 in accordance with a specified wiring pattern by a known photoetching process. Subsequently, the substrate was spin-coated with a varnish of polyimide precursor (PIQ, produced by Hitachi Chemical Co., Ltd.) at a rotational speed of from 1,000 to 5,000 rpm, followed by heating in a nitrogen atmosphere at 100° C. for one hour and at 350° C. for 30 minutes to harden the vanish, to thereby form a first insulating film 9 formed of a polyimide film.
  • The polyimide film was then spin-coated with a negative type liquid resist (OMR-83, produced by TOKYO OHKA KOGYO CO., LTD), followed by hardening at 90° C. for 30 minutes. The resist film thus hardened was then subjected to photoresist patterning, followed by development, and was hardened again in a nitrogen atmosphere at 150° C. for 30 minutes, to thereby form windows in the resist film. [0055]
  • After that, the substrate in such a state was immersed in a mixed solution of hydrazine hydrate and ethylene diamine, to form in the [0056] polyimide film windows 3 for interlayer connection, and then the photoresist was separated from the polyimide film by a separating agent composed of an alkali solution (N303C, produced by TOKYO OHKA KOGYO CO., LTD).
  • After the first insulating [0057] film 9 was thus formed, a second conductive layer 10 was formed of Al by vapor-deposition, followed by patterning by the known photoetching process. At this time, the second conductive layer 10 was electrically connected to the first conductive layer 8 through the windows 3 opened at specified positions for interlayer connection.
  • The above steps were repeated to form a second insulating [0058] layer 11 and a third conductive layer 12, and then an uppermost passivation film 13 was formed of a polyimide base resin (PIQ, produced by Hitachi Chemical Co., Ltd) in the same manner as described above, to thus form multiple wiring layers.
  • [0059] Solder balls 5 made of Sn/Pb (63/37) to be electrically connected to a package substrate were formed in a grid array over the packaging surface of the multiple wiring layers, to form a semiconductor device.
  • Thus, there was obtained a monolithic LSI having multiple wiring layers (a multi-layered wiring structure) formed on the [0060] semiconductor chip 1 and also having terminals, to be connected to a packaging substrate, disposed in a grid array on the uppermost surface of the multiple wiring layers.
  • The monolithic LSI thus obtained was evaluated in terms of temperature cycle testing [one cycle: from (−55° C./10 min) to (+150° C./10 min)], lead inductance, switching noise, and crosstalk. The results are shown in Table 1. [0061]
  • EXAMPLE 2
  • FIG. 5 is a typical sectional view of a semiconductor device according to one example of the present invention, wherein multiple wiring layers [0062] 14 and a buffer layer 7 are formed as a multi-layered wiring structure.
  • First, a copper thin film was formed by sputtering on the surface of a [0063] silicon semiconductor chip 1 having multiple wiring layers formed with a circuit and windows for electric connection. Next, the copper thin film was etched by a specified process to form a wiring. The copper thin film was then stuck with an adhesive sheet formed of a low thermal expansive polyimide film (X952, produced by Hitachi Chemical, Co., Ltd.) applied with an adhesive, followed by hardening the adhesive, and the adhesive sheet was pierced by laser to form specified holes. Via-stads were formed in the specified holes by nonelectrolytic copper plating, and then a copper film was formed on the adhesive film having the holes by sputtering.
  • The above steps were repeated to form multiple wiring layers [0064] 14. A buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi sword-shaped conductor containing buffer layer 7 was adhesively bonded via solder on the packaging surface of the multiple wiring layers by pressing and heating, and terminals composed of solder balls 5 made of Sn/Pb (63/37) were connected and formed on the packaging surface of the buffer layer 7, to thereby obtain a semiconductor device.
  • The semiconductor device thus obtained was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1. [0065]
  • A semiconductor device including two [0066] semiconductor chips 1 mounted on the multiple wiring layers 14 was similarly fabricated, which gave the excellent characteristics comparable to those of the semiconductor device having the single semiconductor chip 1.
  • EXAMPLE 3
  • FIG. 6 is a typical sectional view of a semiconductor device according to one example of the present invention, wherein multiple wiring layers [0067] 14 are connected to a circuit formation surface of a silicon semiconductor chip 1 via a multi-sword shaped conductor containing buffer layer 7.
  • A both side copper-clad laminate (MCLE67, produced by Hitachi Chemical Co., Ltd.) was patterned by etching, and was coated with a permanent resist (Provia 52, produced by Ciba-Geigy Japan Limited), followed by drying, exposure, and development to form photo-via holes, and then the permanent resist was hardened by heating. [0068]
  • Next, the laminate was pieced by drilling to form through-holes, followed by nonelectrolytic copper plating to form a copper layer thereon, and then the copper layer was patterned by etching, to thereby form multiple wiring layers [0069] 14. Solder balls 5 were connected in a grid array onto the packaging surface of the multiple wiring layers 14, and a buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi-sword shaped conductor containing buffer layer 7 was laminated and bonded onto the opposed surface of the multiple wiring layers 14, to thereby obtain a semiconductor device. The semiconductor device was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • EXAMPLE 4
  • FIG. 7 is a typical sectional view of a semiconductor device according to one example of the present invention. A [0070] semiconductor chip 1 was buried in a copper made heat spreader 15 having heat radiation fins and fixed thereto by means of a silicon base adhesive, with the circuit formation surface of the semiconductor chip 1 directed on the packaging side, and a buffer film (ASMAT, produced by NITTO DENKO CORPORATION) as a multi-sword shaped conductor containing buffer layer 7 was similarly buried in the heat spreader 15 and bonded with the circuit formation surface of the semiconductor chip 1. Multiple wiring layers 15 were formed on the packaging surface of the heat spreader 15 in the following manner.
  • First, there were prepared two pieces of both side copper-clad laminates (MCF5000I, produced by Hitachi Chemical Co., Ltd.), in each of which wiring patterns were each formed on both surfaces thereof by a specified etching process. These laminates were adhesively bonded with each other by means of an adhesive (AS2250, produced by Hitachi Chemical Co., Ltd.), and were pieced by laser to form through-holes, followed by electric connection of these laminates by nonelectrolytic plating via the though-holes, to thereby obtain the [0071] multi-layered wiring substrate 14.
  • [0072] Solder balls 5 were connected in a grid array onto the packaging surface of the multi-layered wiring substrate 14, to thereby obtain a semiconductor device. The semiconductor device thus obtained was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1.
  • EXAMPLE 5
  • The [0073] semiconductor device 16 fabricated in the same manner as that in Example 1 was sealed by a transfer molding process using an epoxy resin base mold resin (RM192, produced by Hitachi Chemical Co., Ltd.) as shown in FIG. 8, to obtain a semiconductor device in this example. In addition, the transfer molding condition was as follows:
  • mold temperature: 180° C. [0074]
  • molding pressure: 7 MPa [0075]
  • transfer time: 15 sec [0076]
  • molding time: 90 sec [0077]
  • EXAMPLE 6
  • As shown in FIG. 9, two pieces of the [0078] semiconductor device 16 fabricated in the same manner as that in Example 1 were electrically connected and mounted on a multi-layered wiring substrate 18 formed in the same manner as that in Example 3, to obtain a multi-chip packaging structure in which solder balls 5 were formed in a grid array on the packaging surface of the multi-layered wiring substrate 18.
  • COMPARATIVE EXAMPLE 1
  • A conventional BGA (Ball Grid Array) type semiconductor device (number of pins: 225, size: 27 mm×27 mm) was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1. [0079]
  • COMPARATIVE EXAMPLE 2
  • A conventional QFP (Quad Flat Package) type semiconductor device (number of pins: 208, size: 31 mm×31 mm) was evaluated in terms of temperature cycle testing, lead inductance, switching noise, and crosstalk. The results are shown in Table 1. [0080]
  • When compared with the conventional semiconductor devices, the semiconductor device of the present invention shown in each example does not produce any connection failure in the temperature cycle testing, and is low in inductance, switching noise, and crosstalk per unit length. [0081]
    TABLE 1
    Comparative
    Example Example
    1 2 3 4 1 2
    number of 51 51 51 55 31 22
    terminals per unit
    area (piece/cm2)
    temperature 1000 cycle 0/50 0/50 0/50 0/50  1/50  2/50
    cycle testing* 3000 cycle 0/50 0/50 0/50 1/50 20/50 10/50
    lead inductance 0.25 0.28 0.28 0.30 0.49 0.63
    per unit length
    (nH/mm)
    switching noise 0.30 0.35 0.35 0.40 0.55 0.73
    (V)
    crosstalk (V) 0.04 0.05 0.05 0.07 0.09 0.51

Claims (19)

What is claimed is:
1. A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor chip;
forming a multi-layer wiring structure, having at least one wiring layer, overlying the semiconductor chip, wherein the multi-layer wiring structure includes at least one buffer layer for relieving thermal stress produced between said semiconductor chip and a wiring substrate therefor in packaging the semiconductor chip on the wiring substrate, the at least one wiring layer being positioned so as to be in electrical connection with the semiconductor chip; and
forming ball-like terminals, which are for electrical connection to the wiring substrate, on a surface of the multi-layer wiring structure that is not closest to the semiconductor chip.
2. The method according to
claim 1
, wherein the multi-layer wiring structure is formed such that a first side thereof is closest to a first surface of the semiconductor chip, and wherein the ball-like terminals are provided on a side of the multi-layer wiring structure opposite to said first side thereof.
3. The method according to
claim 1
, wherein said at least one buffer layer has a modulus of elasticity of at most 10 Kg/mm2.
4. The method according to
claim 1
, wherein the multi-layer wiring structure is formed by forming an insulating layer overlying the semiconductor chip, said insulating layer having holes therethrough exposing the semiconductor chip; forming a wiring layer overlying the insulating layer, the wiring layer being in electrical connection with the semiconductor chip; and forming the ball-like terminals in electrical connection with the wiring layer, said insulating layer being the buffer layer for relieving thermal stress.
5. The method according to
claim 4
, wherein said insulating layer is made of an elastomer.
6. The method according to
claim 4
, wherein the insulating layer has a modulus of elasticity of at most 10 Kg/mm2.
7. The method according to
claim 4
, wherein the step of forming the insulating layer includes forming a film of material of the insulating layer and selectively removing the film to form the holes exposing the semiconductor chip.
8. The method according to
claim 4
, wherein the forming of the multi-layer wiring structure includes further steps of alternately forming further insulating layers and further wiring layers, the further insulating layers having holes therethrough such that layers, of the wiring layer and further wiring layers, can be provided in electrical connection with each other.
9. The method according to
claim 8
, wherein the ball-like terminals are formed on a wiring layer, of the wiring layer and further wiring layers, furthest from the semiconductor chip.
10. The method according to
claim 8
, wherein each insulating layer and further insulating layer is made of an elastomer, and constitutes a buffer layer for relieving thermal stress produced between the semiconductor chip and the wiring substrate therefor in packaging the semiconductor chip on the wiring substrate.
11. The method according to
claim 1
, wherein the multi-layer wiring structure is formed by providing a multi-layered wiring sheet; providing a multi-wire, conductor-containing buffer layer, the multi-wire, conductor-containing buffer layer being said at least one buffer layer for relieving thermal stress; and attaching the multi-layered wiring sheet to the semiconductor chip via the multi-wire, conductor-containing buffer layer.
12. The method according to
claim 11
, wherein the ball-like terminals are formed on the multi-layered wiring sheet.
13. The method according to
claim 11
, wherein the multi-layered wiring sheet is formed by adhering a plurality of sheets of wiring to each other, forming windows for inter-layer connection in the plurality of sheets, and performing inter-layer connection.
14. The method according to
claim 11
, wherein the multi-wire, conductor-containing buffer layer is an anisotropic conductive film which has electrical conductivity only in a thickness direction of the buffer layer.
15. The method according to
claim 11
, wherein the multi-wire, conductor-containing buffer layer is a film having through-holes, the through-holes being buried with a conductive material; and wherein in attaching the multi-layered wiring sheet to the semiconductor chip via the multi-wire, conductor-containing buffer layer the conductive material buried in the through-holes is in electrical connection with the semiconductor chip.
16. The method according to
claim 15
, wherein said film having through-holes is made of a polyimide material.
17. The method according to
claim 11
, wherein the step of providing the multi-wire, conductor-containing buffer layer includes casting an elastomer into a vessel in which conducting wires are erected, thereby forming a cast layer containing the conducting wires which constitutes the buffer layer.
18. The method according to
claim 11
, wherein the step of attaching adhesively bonds the multi-layered wiring sheet to the semiconductor chip via the multi-wire, conductor-containing buffer layer.
19. The method according to
claim 1
, comprising the further steps of:
providing the wiring substrate;
positioning the multi-layer wiring structure, having the ball-like terminals formed on a surface thereof, on the wiring substrate, with the ball-like terminals being adjacent the wiring substrate; and
electrically connecting the multi-layer wiring structure to the wiring substrate, via the ball-like terminals, thereby forming a packaging substrate.
US09/884,378 1994-09-20 2001-06-20 Method of making a semiconductor device having a stress relieving mechanism Expired - Fee Related US6423571B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/884,378 US6423571B2 (en) 1994-09-20 2001-06-20 Method of making a semiconductor device having a stress relieving mechanism

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP22467494 1994-09-20
JP6-224674 1994-09-20
US08/809,233 US6028364A (en) 1994-09-20 1995-04-12 Semiconductor device having a stress relieving mechanism
US48289100A 2000-01-14 2000-01-14
US09/884,378 US6423571B2 (en) 1994-09-20 2001-06-20 Method of making a semiconductor device having a stress relieving mechanism

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US48289100A Division 1994-09-20 2000-01-14

Publications (2)

Publication Number Publication Date
US20010051393A1 true US20010051393A1 (en) 2001-12-13
US6423571B2 US6423571B2 (en) 2002-07-23

Family

ID=27330938

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/884,378 Expired - Fee Related US6423571B2 (en) 1994-09-20 2001-06-20 Method of making a semiconductor device having a stress relieving mechanism

Country Status (1)

Country Link
US (1) US6423571B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472293B2 (en) * 1999-04-13 2002-10-29 Oki Electric Industry Co., Ltd. Method for manufacturing an interconnect structure for stacked semiconductor device
US20060290002A1 (en) * 2005-06-28 2006-12-28 Arana Leonel R Method of forming through-silicon vias with stress buffer collars and resulting devices
US20090109642A1 (en) * 2007-10-26 2009-04-30 Samsung Electronics Co., Ltd. Semiconductor modules and electronic devices using the same
US20090273075A1 (en) * 2008-05-05 2009-11-05 Infineon Technologies Ag Semiconductor device and manufacturing of the semiconductor device
US20160027725A1 (en) * 2014-07-25 2016-01-28 Ibiden Co., Ltd. Multilayer wiring board and method for manufacturing same
US9893016B2 (en) 2014-10-10 2018-02-13 Ibiden Co., Ltd. Multilayer wiring board having wiring structure for mounting multiple electronic components and method for manufacturing the same
CN110767613A (en) * 2018-07-27 2020-02-07 三星电子株式会社 Semiconductor package and antenna module including the same

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4680410B2 (en) * 2001-04-24 2011-05-11 日本特殊陶業株式会社 Wiring board
JP2003124393A (en) * 2001-10-17 2003-04-25 Hitachi Ltd Semiconductor device and manufacturing method therefor
US6690580B1 (en) * 2002-03-07 2004-02-10 Amd, Inc. Integrated circuit structure with dielectric islands in metallized regions
US7265045B2 (en) 2002-10-24 2007-09-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8804339B2 (en) * 2011-02-28 2014-08-12 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronics assemblies, insulated metal substrate assemblies, and vehicles incorporating the same
US8654541B2 (en) 2011-03-24 2014-02-18 Toyota Motor Engineering & Manufacturing North America, Inc. Three-dimensional power electronics packages
US9147662B1 (en) * 2013-12-20 2015-09-29 Stats Chippac Ltd. Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof
US9673287B2 (en) 2014-12-15 2017-06-06 Infineon Technologies Americas Corp. Reliable and robust electrical contact
US11387213B2 (en) * 2020-06-05 2022-07-12 Advanced Semiconductor Engineering, Inc. Method for manufacturing a semiconductor package

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3479463D1 (en) 1983-03-29 1989-09-21 Nec Corp High density lsi package for logic circuits
JPS62136865A (en) 1985-12-11 1987-06-19 Hitachi Ltd Module mounting structure
JPS62287658A (en) 1986-06-06 1987-12-14 Hitachi Ltd Ceramic multilayered circuit board and semiconductor module
JPS6461934A (en) 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
JPH0756887B2 (en) 1988-04-04 1995-06-14 株式会社日立製作所 Semiconductor package and computer using the same
US5220199A (en) 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JPH03116838A (en) 1989-09-29 1991-05-17 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JP2510747B2 (en) 1990-02-26 1996-06-26 株式会社日立製作所 Mounting board
EP0509825A3 (en) 1991-04-16 1993-11-24 Nec Corp Package structure for semiconductor device
JP2966972B2 (en) 1991-07-05 1999-10-25 株式会社日立製作所 Semiconductor chip carrier, module mounting the same, and electronic device incorporating the same
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US5550408A (en) 1992-11-18 1996-08-27 Matsushita Electronics Corporation Semiconductor device
TW256013B (en) 1994-03-18 1995-09-01 Hitachi Seisakusyo Kk Installation board
IL110261A0 (en) * 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
JPH0846136A (en) 1994-07-26 1996-02-16 Fujitsu Ltd Semiconductor device
US5635767A (en) 1995-06-02 1997-06-03 Motorola, Inc. Semiconductor device having built-in high frequency bypass capacitor
JP2812358B2 (en) 1996-03-18 1998-10-22 日本電気株式会社 LSI package and LSI package manufacturing method
JP3116838B2 (en) 1996-10-21 2000-12-11 日本電気株式会社 Semiconductor device
US6232131B1 (en) * 1998-06-24 2001-05-15 Matsushita Electronics Corporation Method for manufacturing semiconductor device with ferroelectric capacitors including multiple annealing steps

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472293B2 (en) * 1999-04-13 2002-10-29 Oki Electric Industry Co., Ltd. Method for manufacturing an interconnect structure for stacked semiconductor device
US20060290002A1 (en) * 2005-06-28 2006-12-28 Arana Leonel R Method of forming through-silicon vias with stress buffer collars and resulting devices
US7402515B2 (en) * 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US20080251932A1 (en) * 2005-06-28 2008-10-16 Arana Leonel R Method of forming through-silicon vias with stress buffer collars and resulting devices
US20090109642A1 (en) * 2007-10-26 2009-04-30 Samsung Electronics Co., Ltd. Semiconductor modules and electronic devices using the same
US20090273075A1 (en) * 2008-05-05 2009-11-05 Infineon Technologies Ag Semiconductor device and manufacturing of the semiconductor device
US8264085B2 (en) * 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
US8669175B2 (en) 2008-05-05 2014-03-11 Infineon Technologies Ag Semiconductor device and manufacturing of the semiconductor device
US20160027725A1 (en) * 2014-07-25 2016-01-28 Ibiden Co., Ltd. Multilayer wiring board and method for manufacturing same
US9837342B2 (en) * 2014-07-25 2017-12-05 Ibiden Co., Ltd. Multilayer wiring board and method for manufacturing same
US9893016B2 (en) 2014-10-10 2018-02-13 Ibiden Co., Ltd. Multilayer wiring board having wiring structure for mounting multiple electronic components and method for manufacturing the same
CN110767613A (en) * 2018-07-27 2020-02-07 三星电子株式会社 Semiconductor package and antenna module including the same

Also Published As

Publication number Publication date
US6423571B2 (en) 2002-07-23

Similar Documents

Publication Publication Date Title
US6028364A (en) Semiconductor device having a stress relieving mechanism
US6423571B2 (en) Method of making a semiconductor device having a stress relieving mechanism
EP0567814B1 (en) Printed circuit board for mounting semiconductors and other electronic components
US4709468A (en) Method for producing an integrated circuit product having a polyimide film interconnection structure
US5147210A (en) Polymer film interconnect
KR100274333B1 (en) conductive layer adhesive anisotropic concuctive sheet and wiring board using such a sheet
US8222747B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
US7276400B2 (en) Methods of making microelectronic packages with conductive elastomeric posts
US4890157A (en) Integrated circuit product having a polyimide film interconnection structure
US6271056B1 (en) Stacked semiconductor package and method of fabrication
KR100442880B1 (en) Stacked semiconductor module and manufacturing method thereof
US7098533B2 (en) Printed circuit board with a heat dissipation element and package comprising the printed circuit board
JP2003522401A (en) Stacked integrated circuit package
US6458627B1 (en) Semiconductor chip package and method of fabricating same
KR100257926B1 (en) Multi-layer film for circuit board and multi-layer circuit board using the same and pakage for semiconductor device
EP0843357B1 (en) Method of manufacturing a grid array semiconductor package
US6708398B2 (en) Substrate for use in package of semiconductor device, semiconductor package using the substrate, and methods for manufacturing the substrate and the semiconductor package
US6709899B2 (en) Methods of making microelectronic assemblies having conductive elastomeric posts
US6432748B1 (en) Substrate structure for semiconductor package and manufacturing method thereof
JP3378171B2 (en) Semiconductor package manufacturing method
JP3691335B2 (en) Circuit device manufacturing method
JP3549316B2 (en) Wiring board
JP2785536B2 (en) Multi-chip module and manufacturing method thereof
JPH07297320A (en) Bga type semiconductor device
KR19980068016A (en) Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100723