CN100377361C - 图像感应器模块与晶圆级封装的结构及其形成方法 - Google Patents

图像感应器模块与晶圆级封装的结构及其形成方法 Download PDF

Info

Publication number
CN100377361C
CN100377361C CNB2004100592937A CN200410059293A CN100377361C CN 100377361 C CN100377361 C CN 100377361C CN B2004100592937 A CNB2004100592937 A CN B2004100592937A CN 200410059293 A CN200410059293 A CN 200410059293A CN 100377361 C CN100377361 C CN 100377361C
Authority
CN
China
Prior art keywords
tube core
layer
mentioned
dielectric layer
contact conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2004100592937A
Other languages
English (en)
Other versions
CN1691343A (zh
Inventor
杨文焜
杨文彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN1691343A publication Critical patent/CN1691343A/zh
Application granted granted Critical
Publication of CN100377361C publication Critical patent/CN100377361C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02325—Optical elements or arrangements associated with the device the optical elements not being integrated nor being directly associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Studio Devices (AREA)

Abstract

本发明一种图像感应器模块与晶圆级封装的结构及其形成方法，其中该图像感应器模块包括：一绝缘基板；一晶圆级封装，上述晶圆级封装附着于上述绝缘基板之上，上述晶圆级封装具有一多数个图像感应器与一多数个金属焊接球；一镜架，上述镜架置于上述图像感应器管芯之上，上述镜架内置有一多数个镜片；以及，一软板，上述镜架置于该软板之中，并且上述软板具有多数个焊点与上述多数个金属焊接球作电性耦合以利于传输上述多数个图像感应器的功能。上述图像感应器可以与被动组件或其它具有并列结构或堆栈结构的管芯一起封装。

Description

图像感应器模块与晶圆级封装的结构及其形成方法
技术领域
本发明涉及图像感应器模块，特别是一种可以降低价格、提高封装结构的优良率(yield)与可靠度(reliability)的图像感应器模块与晶圆级封装的结构及其形成方法。
背景技术
半导体的技术已经发展得相当的迅速，特别是半导体管芯(dies)有朝向小型化的趋势。然而，对于半导体管芯(dies)的功能的需求相对的具有多样化的趋势。也就是说，上述半导体管芯(dies)在一个很小的区域中必须具有更多的输入/输出垫(I/O pads)，因而使得引线(pins)的密度也快速地提高了。这会导致上述半导体管芯(dies)的封装变得越来越困难，并且优良率也因此降低了。
上述封装结构的主要目的在于保护上述管芯免于受到外在的损害。再者，由于上述管芯所产生的热必须有效率地透过上述封装结构来扩散以确保上述管芯的运作。
早期的导线架封装技术已经不适合引线(pins)密度过高的更进步的半导体管芯。因此，一新的球数组(Ball Grid Array：BGA)封装技术已经被发展出来，其可以满足上述更进步的半导体管芯的封装需求。上述球数组封装具有一个好处，也就是它的球形引线(pins)具有比上述导线架封装来得小之间距(pitch)，并且上述引线(pins)不容易损害与变形。此外，较短的信号传递距离可以有益于提升操作频率以符合更快效率的需求。大部分的封装技术都是先将一晶圆上的管芯分离成为个别的管芯，然后再在封装与测试上述个别的管芯。另外一种称为晶圆型态封装(waferlevel package：WLP)的封装技术可以在分离个别的管芯的前就封装上述晶圆上的管芯。上述晶圆型态封装(wafer level package：WLP)具有一些好处，例如：一个较短的生产周期(cycle time)、较低的价格以及不需要填充物(under-fill)或铸模(molding)。
上述管芯例如为图像感应器。目前，图像感应器模块是利用COB或LCC的方法来形成。其中，COB方法的缺点之一是为于制造期间会由于传感器区域上的粒子(particle)无法清洗而造成优良率降低的情况产生。而LCC的方法由于材料的因素使得它的封装价格太高，并且封装期间也会由于传感器区域上的粒子(particle)而造成优良率降低的情况产生。此外，ShellCase(公司名称)也开发了晶圆型态封装(wafer level package：WLP)技术，若以该公司的技术来制造图像感应管芯封装，一方面由于其需要二个玻璃板，其材料成本偏高，另一方面由于其制程的复杂使得它的封装价格高居不下。而且由于其绝缘层的磨损(wear out)导致透光度不佳，进一步也使得其可靠度(reliability)降低。
因此，鉴于上述现有技术所提到的问题而提出本发明，而本发明的目的是在于提供一崭新的图像感应器模块。
发明内容
鉴于上述现有技术所提到的问题而提出本发明，而本发明的目的是提供图像感应器模块与晶圆级封装的结构及其形成方法。
此外，本发明的目的是提供图像感应器模块以利于晶圆级封装的最终测试(final testing)。
再者，本发明的再一目的是降低封装结构的价格。
另外，本发明的又一目的是提高封装结构的优良率(yield)与可靠度(reliability)。除了可以应用于半导体产业，还可应用于液晶显示器产业。
如上所述，本发明的目的是提供一种图像感应器模块，该图像感应器模块包括：一绝缘基板；一晶圆级封装，上述晶圆级封装附着在上述绝缘基板之上，上述晶圆级封装具有一多数个图像感应管芯与一多数个金属焊接球；一镜架，上述镜架置于上述图像感应管芯之上，上述镜架内置有一多数个镜片；以及，一软板，上述镜架置于该软板之中，并且上述软板具有多数个焊点与上述多数个金属焊接球作电性耦合以利于传输上述多数个图像感应管芯的功能。上述图像感应管芯可以与被动组件或其它具有并列结构或堆栈结构的管芯一起封装。
本发明也提供一种晶圆级封装结构。上述封装结构包括：一绝缘基板、第一管芯与第二管芯、第一介电层、第二介电层、接触导电层、绝缘层与焊接球。上述第一管芯与第二管芯附着到上述绝缘基板之上。上述第一介电层形成于上述绝缘基板之上，其是在该绝缘基板之上的上述第一管芯与该第二管芯的外填满上述第一介电层。上述第二介电层形成于上述第二管芯之上。上述接触导电层形成于上述第一管芯的第一金属垫与第二管芯的第二金属垫之上完全覆盖住上述第一与第二金属垫，上述接触导电层分别与上述第一金属垫、第二金属垫作电性耦合。上述绝缘层形成于上述接触导电层之上，并且上述绝缘层具有开口形成于上述接触导电层之上。上述焊接球是利用锻烧的方法而形成于上述开口之上，上述焊接球分别与上述接触导电层耦合。上述第一管芯的型态可以选自DSP管芯、主动管芯、被动管芯、支撑管芯、CPU管芯或处理器管芯；而上述第二管芯为互补式金氧半导体图像感应管芯。上述图像感应管芯与DSP管芯、主动管芯、被动管芯、支撑管芯、CPU管芯或处理器管芯是为并列结构的封装。
本发明还提供一种晶圆级封装结构。上述封装结构包括：一绝缘基板、第一管芯与第二管芯、第一介电层、第二介电层、第三介电层、第一与第二接触导电层、绝缘层与焊接球。上述第一管芯附着到上述绝缘基板之上。上述第一介电层形成于上述绝缘基板之上，其是在上述绝缘基板之上的第一管芯的外填满上述第一介电层。上述第一接触导电层形成于上述第一管芯的第一金属垫之上完全覆盖住上述第一金属垫，上述第一接触导电层分别与上述第一金属垫作电性耦合。上述第二管芯附着到上述第一管芯之上。上述第二介电层形成于上述第一介电层之上，其是在上述第二管芯的外填满上述第二介电层，并且上述第二介电层具有介层洞形成于该第一接触导电层之上。上述第三介电层形成于上述第二管芯之上。上述第二接触导电层填满上述介层洞并形成于上述第二管芯的第二金属垫之上以覆盖住该第二金属垫，上述第二接触导电层与上述第二金属垫、第一接触导电层作电性耦合。上述绝缘层形成于上述第二接触导电层之上，并且上述绝缘层具有开口形成于上述第二接触导电层之上。上述焊接球是利用锻烧的方法而形成于上述开口之上，上述焊接球分别与上述第二接触导电层耦合。上述第一管芯的型态可以选自DSP管芯、主动管芯、被动管芯、支撑管芯、CPU管芯或处理器管芯；而上述第二管芯为互补式金氧半导体图像感应器。上述图像感应器与DSP管芯、主动管芯、被动管芯、支撑管芯、CPU管芯或处理器管芯是为堆栈结构的封装。
本发明又提供一种晶圆级封装结构的形成方法。上述方法包括：首先，形成一第一光阻图案于一晶圆上的多数个管芯的金属垫之上以覆盖住该金属垫；接着，形成一水玻璃(二氧化硅)于上述第一光阻图案与多数个管芯之上；然后，烘烤上述水玻璃；之后，去除剩余的上述第一光阻层；接着，切割上述晶圆上的多数个管芯以形成个别的管芯；然后，选取良好的管芯并附着该管芯到一绝缘基板之上；之后，烘烤上述绝缘基板；接着，形成一材料层于上述绝缘基板之上，其是在该绝缘基板之上的多数个管芯之间填满该材料层；然后，烘烤上述材料层；之后，形成一第二介电层于上述第一材料层与金属垫之上；接着，蚀刻上述金属垫之上的第二介电层的部分区域以形成第一开口；然后，烘烤上述第二介电层；之后，形成一接触导电层于上述第一开口之上以分别与上述金属垫作电性耦合；接着，形成一第二光阻层于上述第二介电层与接触导电层之上；然后，去除上述第二光阻层的一部分区域以形成一第二光阻图案并且暴露上述接触导电层以形成第二开口；之后，形成导线层于上述第二光阻图案与第二开口之上，使得上述导线层分别与上述接触导电层耦合；接着，去除剩余的上述第二光阻层；然后，形成一绝缘层于上述导线层与第二介电层之上；之后，去除上述导线层上的绝缘层的一部分区域以形成第三开口；接着，烘烤上述绝缘层；最后，锻烧焊接球于上述第三开口之上。
附图说明
图1为根据本发明的一图像感应器模块的示意图；
图2为根据本发明的一具有二个管芯的并列结构封装示意图；
图3为根据本发明的一具有二个管芯的堆栈结构封装示意图；
图4A～图4J为根据本发明的一晶圆级封装结构的形成方法示意图；
图5为本发明多芯片尺度封装(Multi-CSP)的最终测试(finaltesting)示意图；
图6为显示依据本发明实施例可通过以应用于液晶显示器面板产业示意图。
图标符号对照表
绝缘基板100、200、300、405
晶圆级封装101
镜架102
软板103
图像感应器104、201、301
管芯105、202、302、400
附着材料106、203、310、406
焊锡球(solder balls)107、208、307、416
介电层108、110、205、207、303、304、311、403、409
接触导电层109、206、305a、305b、410
滤光层(filter)111
绝缘层112、209、306、414
镜片113、114
金属垫115、116、204、210、308、309、401
电性结构117
介层洞312
第一光阻图案402
切割线404、417
材料层407
第一开口408
第二光阻图案411
第二开口412
导线层413
第三开口415
玻璃基板600
芯片尺度封装(CSP)601
具体实施方式
本发明的一些实施例将于此详细地描述。本发明不受限于实施例，也可以在一宽广的涵盖其它均等范围的其它实施例，并且本发明的范围当以所述的专利范围为准。
然而，不同构成要素的组件并不依实际的尺寸来显示。一些相关组件的大小是扩大的，并且无意义的部分没有画出来，这样比较容易提供本发明的一更清楚的描述与理解。
本发明的管芯可以与被动组件(例如：电容)或其它具有并列结构或堆栈结构的管芯一起封装。除可以使用于半导体产业，亦可使用于液晶显示器设备来完成集成电路封装。
如上所述，本发明的目的在于提供一种图像感应器模块，如图1所示。本发明的晶圆级封装部分结构剖面以101表示。上述图像感应器模块包括：一绝缘基板100、一晶圆级封装101、一镜架102与一软板103。上述绝缘基板100的材质可以是玻璃、硅、陶磁或石英晶体材料等等，并且其具有圆形或矩形的形状。上述晶圆级封装101具有一多数个图像感应管芯104与其它具有并列结构的管芯105，例如数字信号处理管芯(digital signalprocess；DSP)。须注意的是为上述管芯105为选择性的配置。上述图像感应管芯104可以为互补式金氧半导体图像感应管芯。上述管芯105的型态可以选自DSP管芯、主动(active)管芯、被动(passive)管芯、支撑(support)管芯、CPU管芯或处理器(processor)管芯等等。上述图像感应管芯104与管芯105是以并列的方式一起封装。上述晶圆级封装101是利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附着材料106而附着上述图像感应管芯104与管芯105到上述绝缘基板100之上。上述晶圆级封装101具有一多数个金属焊接球107，做为信号传导机制，上述金属焊接球107例如为焊锡球(solder balls)107。
一介电层108形成于上述绝缘基板100之上，其是在绝缘基板100之上之上述图像感应管芯104与管芯105的外填满上述介电层108。上述介电层108的材质可以为硅胶(Silicon rubber)。
接触导电层109形成于上述图像感应管芯104的金属垫115与管芯105的金属垫116之上，以完全覆盖住上述金属垫115与金属垫116。也就是说，上述接触导电层109分别与上述金属垫115与金属垫116作电性耦合。上述接触导电层109的材质可以包括镍(Ni)、铜(Cu)、金(Au)与其组合。
另外，一膜层110披覆于上述图像感应管芯104之上。上述膜层110的材质为二氧化硅(SiO2)或称水玻璃、或三氧化铝，其是用来作为保护膜(protection film)之用，例如采用旋涂方式形成。控制上述膜层110厚度使其不会影响图像感应管芯104的运作，厚度约为20微米(μ)以内。上述膜层110上可包含一滤光层(filtering film)111例如是一红外线滤光层(IR filter)，可以用来做为滤光波之用。
一绝缘层112形成于上述接触导电层109之上，并且上述绝缘层112具有开口形成于上述接触导电层109之上。上述绝缘层112不得遮住图像感应器104以利于感测图像。上述绝缘层112的材质可以包括环氧化物层、树脂与其组合。
上述镜架102置于上述图像感应管芯104之上，并且镜架102内置有一透镜组包含镜片113、114。上述镜架102置于上述软板103之中，利用上述软板103上的多数个电性结构117与上述焊锡球(solder balls)107作电性耦合，以利于传递信号。因此，本发明的镜架102与软板103的组合具有探针卡(probe card)的功能，其可以作为多芯片尺度封装(Multi-CSP)的最终测试(final testing)，请参阅图5。
如上所述，本发明还提供一种晶圆级封装结构，如图2所示。上述封装结构包括：一绝缘基板200、图像感应管芯201与管芯202、第一介电层205、第二介电层207、接触导电层206、绝缘层209与焊接球208。上述绝缘基板200的材质可以是玻璃、硅、陶磁或晶体材料等等，并且其具有圆形或矩形的形状。上述图像感应管芯201与管芯202是以并列的方式一起封装。上述图像感应管芯201与管芯202是利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附着材料203而附着到上述绝缘基板200之上。上述第一介电层205形成于上述绝缘基板200之上，其是在绝缘基板200之上之上述图像感应管芯201与管芯202的外填满上述第一介电层205。上述第一介电层205的材质可以为硅胶(Silicon rubber)。
上述第二介电层207形成于上述图像感应管芯201之上，其覆盖了上述图像感应管芯201的感光区域。上述第二介电层207的材质可以为二氧化硅(Si02)，其是用来作为保护模(protection film)之用。另外，一滤光层(filtering film)可以形成于上述图像感应管芯201之上的上述第二介电层207之上。上述滤光层(filtering film)例如是一红外线滤光层(IR filtering layer)，其可以用来滤波之用。
上述接触导电层206形成于上述图像感应管芯201的金属垫210与管芯202的金属垫204之上，以完全覆盖住上述金属垫210与金属垫204。也就是说，上述接触导电层206分别与上述金属垫210与金属垫204作电性耦合。上述接触导电层206的材质可以包括镍(Ni)、铜(Cu)、金(Au)与其组合。上述金属垫210与金属垫204例如为铝垫(Al pad)。上述绝缘层209形成于上述接触导电层206之上，并且上述绝缘层209具有开口形成于上述接触导电层206之上。上述绝缘层209的材质可以包括环氧化物层(epoxy)、树脂或SINR(一种Siloxane polymer)或BCB。上述金属焊接球208是利用锻烧的方法而形成于上述开口之上，使得上述金属焊接球208分别与上述接触导电层206耦合。上述金属焊接球208例如为焊锡球(so1der balls)208。
上述管芯202的型态可以选自DSP管芯、主动(active)管芯、被动(passive)管芯、支撑(support)管芯、CPU管芯或处理器(processor)管芯；而上述图像感应管芯201可以为互补式金氧半导体图像感应管芯。上述图像感应管芯201与管芯202是为并列结构的封装。
此外，本发明还提供另一种晶圆级封装结构，如图3所示。其特征是为芯片采用堆栈方式建构。上述封装结构包括：一绝缘基板300、图像感应管芯301与管芯302、第一介电层303、第二介电层304、第三介电层311、接触导电层305a、305b、绝缘层306与焊接球307。上述绝缘基板300的材质可以是玻璃、硅、陶磁或石英晶体材料等等，并且其具有圆形或矩形的形状。上述图像感应管芯301与管芯302是以堆栈的方式一起封装。上述管芯302是利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附着材料310a而附着到上述绝缘基板300之上。上述第一介电层303形成于上述绝缘基板300之上，其是在上述绝缘基板300之上的上述管芯302的外填满上述第一介电层303。上述第一介电层303的材质可以为硅胶(Silicon rubber)。
上述接触导电层305a形成于上述管芯302的金属垫309之上完全覆盖住上述金属垫309，上述接触导电层305a分别与上述金属垫309作电性耦合。上述图像感应管芯301是利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附着材料310b而附着到上述管芯302之上。上述第二介电层304形成于上述第一介电层303之上，其是在上述图像感应管芯301的外填满上述第二介电层304，并且上述第二介电层304具有介层洞312形成于接触导电层305a之上。上述第二介电层304的材质可以为二氧化硅(SiO2)。
此外，第三介电层311形成于上述图像感应管芯301之上，其覆盖了上述图像感应管芯301的感光区域。然而，上述第三介电层311不会影响图像感应管芯301的的运作。上述第三介电层311的材质可以为二氧化硅(SiO2)，其是用来作为保护模(protection film)之用。另外，一滤光层(filtering film)可以形成于上述图像感应管芯301之上之上述第三介电层311之上。上述滤光层(filtering film)例如是一红外线滤光层(IR filtering layer)，其可以用来滤波之用。
上述接触导电层305b填满上述介层洞312并形成于上述图像感应管芯301的金属垫308之上完全覆盖住该金属垫308。也就是说，上述接触导电层305b与上述金属垫308、接触导电层305a作电性耦合。上述接触导电层305a、305b的材质可以包括镍(Ni)、铜(Cu)、金(Au)与其组合。上述金属垫308与金属垫309例如为铝垫(Al pad)。上述绝缘层306形成于上述接触导电层305b之上，并且上述绝缘层306具有开口(未图示)形成于上述接触导电层305b之上。上述绝缘层306的材质可以包括环氧化物层、树脂与其组合。
上述金属焊接球307是利用焊接的方法而形成于上述开口之上，上述金属焊接球307分别与上述接触导电层305b耦合。上述金属焊接球307例如为焊锡球(solder balls)307。
上述管芯302的型态可以选自DSP管芯、主动(active)管芯、被动(passive)管芯、支撑(support)管芯、CPU管芯或处理器(processor)管芯；而上述图像感应管芯301可以为互补式金氧半导体图像感应管芯。上述图像感应管芯301与管芯302是为堆栈结构的封装。
图4A～图4J为根据本发明的一晶圆级封装结构的形成方法示意图。
再者，本发明又提供一种晶圆级封装结构的形成方法。上述方法包括：首先，形成一第一光阻图案402于一晶圆上的管芯400的金属垫401之上完全覆盖住该金属垫401，请参考图4A。接着，形成一第一介电层于上述第一光阻图案402间与管芯400之上。然后，烘烤上述第一介电层。之后，去除剩余的上述第一光阻层402以形成介电层403。上述介电层403的材质为二氧化硅(SiO2)，其是用来作为保护膜(protection film)的用。例如采用旋涂方式形成的氧化层或称水玻璃。接着，沿着切割线404切割上述晶圆上的多数个管芯400以形成个别的管芯，如图4B所示。另外，一滤光层(filtering film)可以形成于上述介电层403之上。上述滤光层(filtering film)例如是一红外线滤光层(IR filtering layer)，其可以用来滤波之用。请参照上述的实施例。
上述去除剩余的第一光阻层402步骤之后，可以再通过由背磨(backlapping)上述完成制造硅晶圆而得到一厚度约100～300微米(micron)的上述完成制造的硅晶圆。上述的完成制造的硅晶圆厚度可以很容易地切割硅晶圆上的管芯400以成为个别的管芯。如果不经过背磨(backlapping)而上述的完成制造硅晶圆不会很难切割的话，上述背磨(backlapping)步骤是可以被省略的。上述管芯400包括至少二种型态的管芯。
然后，上述个别管芯接着经过测试从其中选择标准的良好管芯400。然后，拿取上述标准良好的管芯400重新置放在一绝缘基板405之上，使得二个相邻的管芯之间具有一个更宽广或适度的距离，并且利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附着材料406附着上述管芯400到上述绝缘基板405之上。之后，通过由UV光或热能来烘烤上述绝缘基板405，如图4C所示。上述附着材料406是利用涂布方式形成在上述绝缘基板405之上，并且上述附着材料406的厚度最好是在20～60微米(micron)之间。上述绝缘基板405的材质可以是玻璃、硅、陶磁或晶体材料等等，并且其具有圆形或矩形的形状。
上述管芯400具有输入/输出(I/O)垫401形成于上表面。本发明的附着材料406最好是具有良好的热传导材料，这样才可以使得上述起因于管芯400与绝缘基板405之间温度差异所产生的问题(例如应力)被避免。
接着，形成一材料层407于上述绝缘基板405之上，其是在该绝缘基板405之上的管芯400之间填满上述材料层407。并且上述材料层407与管芯400的表面在大约相同的高度，如图4D所示。然后，通过由UV或热能烘烤上述材料层407。上述材料层407可以通过由一网印的方法或一微影的方法来形成。上述材料层407可以用来作为一缓冲层以降低由于温度等所产生的应力。上述材料层407可以是一UV与/或热烘烤材料，例如：硅胶、环氧化物层、树脂、BCB等等。
之后，第二介电层(未图示)可涂布形成于上述材料层407与金属垫401之上。上述第二介电层的材料可以是二氧化硅。
接着，利用一光罩来去除上述金属垫401之上的第二介电层的部分区域以形成第一开口408于上述金属垫401之上，然后，通过由UV或热能来烘烤上述介电层409，如图4E所示。此外，选择性地利用电浆蚀刻(RIE)来清除上述金属垫401的表面以确保没有残留的材料留在上述金属垫401之上。
之后，形成一接触导电层410于上述第一开口408之上以分别与上述金属垫401作电性耦合，如图4F所示。上述接触导电层410的较佳材料是钛(Ti)、铜(Cu)或其组合。上述接触导电层410可以通过由一物理方法、化学方法或其组合的形成方式来形成，上述形成方法例如：化学气相沉积、物理气相沉积、溅镀与蒸镀。
接着，形成一第二光阻层(未图示)于上述介电层409与接触导电层410之上。然后，通过由利用一光罩的曝光显影去除上述第二光阻层的一部分区域以形成一第二光阻图案411并且暴露上述接触导电层410以形成第二开口412，如图4图所示。
之后，通过由蒸镀方法，导线层413形成于上述第二开口412之上，使得上述导线层413分别与上述接触导电层耦合410，如图4H所示。上述导线层413的材料较佳的是镍(Ni)、铜(Cu)、金(Au)与其组合。此称为重新线路分布层(re-distribution layer；RDL)
接着，去除剩余的上述第二光阻层411。然后，形成一绝缘层(未图标)于上述导线层413与介电层409之上。之后，去除上述导线层413上的绝缘层的一部分区域以形成绝缘层414与第三开口415于上述导线层413之上，如图4I所示。上述绝缘层可以通过由旋转涂布或网印的方式来形成。
本发明可选择性地形成一环氧化物层(未图示)于上述绝缘基板405的背表面的步骤。
接着，烘烤上述绝缘层414。然后，焊锡球(solder balls)416形成于上述第三开口415之上，如图4J所示。上述焊锡球416可以通过由一网印的方法置放于上述第三开口415之上，并且通过由一红外线回流(IRreflow)的方法将焊锡球416与上述导线层413的表面连接在一起。
最后，前面所述的封装绝缘基板405沿着切割线417进行切割以隔绝个别的封装集成电路。
由此，根据本发明，上述的图像感应器模块与晶圆级封装结构可以降低上述封装结构的价格，并且提高上述封装结构的优良率。此外，本发明的封装大小可以很容易地调整以适合测试设备、封装设备等等。
此外，本发明除可以使用于半导体产业设备于封装上，亦可以使用于液晶显示器面板设备来完成IC封装上。请参阅图6，其显示依据上述本发明实施例的可通过以应用于液晶显示器面板产业示意图。芯片尺度封装(CSP)601形成于玻璃基板600之上。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张的专利权利范围。其专利保护范围当视后附的申请专利范围及其等同领域而定。凡熟悉此领域的技艺者，在不脱离本专利精神或范围内，所作的更动或润饰，均属于本发明所揭示精神下所完成的等效改变或设计，且应包含在下述的申请专利范围内。

Claims (10)

1.一种图像感应器模块，其特征在于包括：
一绝缘基板；
一图像感应管芯，附着于该绝缘基板之上，其中该图像感应管芯具有金属垫，该金属垫与多数个金属焊接球电性耦合；
一保护膜，配置于该图像感应管芯之上；
一镜架，该镜架配置于该图像感应管芯之上，该镜架内置有一多数个镜片；以及
一软板，该镜架置于该软板之中，并且该软板具有多数个导电机制与该多数个金属焊接球作电性耦合以利信号传递；
其中该绝缘基板用以承载该图像感测管芯，该绝缘基板的表面上无预先形成的电路。
2.如权利要求1所述的图像感应器模块，其特征在于：该保护膜为旋涂二氧化硅或三氧化铝；其中该图像感应器模块包含第二管芯与该图像感应管芯构成并列结构或堆栈结构；其中该第二管芯的型态选自DSP管芯、主动管芯、被动管芯、支撑管芯、CPU管芯或处理器管芯；其中该绝缘基板的材质为玻璃、硅、陶瓷或石英晶体。
3.如权利要求2所述的图像感应器模块，其特征在于包含：
一形成于该绝缘基板之上的第一介电层，其是在该绝缘基板之上的该图像感应管芯与该第二管芯间填满该第一介电层；
一形成于该第二管芯之上的第二介电层；
一形成于该图像感应管芯的第一金属垫与该第二管芯的第二金属垫之上以覆盖住该第一与第二金属垫的接触导电层，该接触导电层分别与该第一金属垫、该第二金属垫作电性耦合；
一形成于该接触导电层之上的绝缘层，并且该绝缘层具有开口形成于该接触导电层之上；以及
于该开口之上导电焊锡球，该焊接球分别与该接触导电层耦合。
4.如权利要求3所述的图像感应器模块，其特征在于：该图像感应管芯为互补式金氧半导体图像感应管芯；包含一滤光膜配置于该保护膜之上；其中该第一介电层的材质为硅胶；其中该第二介电层的材质为环氧化物、树脂、SINR或BCB；其中该滤光膜是一红外线滤光层；其中该接触导电层的材质包括镍、铜、金与其组合；其中该绝缘层的材质包括环氧化物层、树脂、硅胶与其组合。
5.如权利要求2所述的图像感应器模块，其特征在于包括：
一形成于该绝缘基板之上的第一介电层，其是在该绝缘基板之上的该第二管芯的外填满该第一介电层；
一形成于该第二管芯的第一金属垫之上完全覆盖住该第一金属垫的第一接触导电层，该第一接触导电层分别与该第一金属垫作电性耦合；
一堆栈附着到该第二管芯的图像感应管芯；
一形成于该第一介电层之上的第二介电层，其是在该图像感应管芯之外填满该第二介电层，并且该第二介电层具有介层洞形成于该第一接触导电层之上；
一形成于该图像感应管芯之上的第三介电层；
一填满该介层洞并形成于该图像感应管芯的一第二金属垫之上以覆盖住该第二金属垫的第二接触导电层，该第二接触导电层与该第二金属垫、该第一接触导电层作电性耦合；
一形成于该第二接触导电层之上的绝缘层，并且该绝缘层具有开口形成于该第二接触导电层之上；以及
于该开口之上的焊接球，该焊接球分别与该第二接触导电层耦合。
6.如权利要求5所述的图像感应器模块，其特征在于：该第一介电层的材质为硅胶；其中该第二介电层的材质为聚乙醯、BT、SINR或环氧化物层；其中该第三介电层的材质为PI或BT或SINR；其中该第一与第二接触导电层的材质包括镍、铜、金与其组合；其中该绝缘层的材质包括环氧化物层、树脂与其组合。
7.一种晶圆级封装结构的形成方法，其特征在于包括：
形成一第一光阻图案于一晶圆上的多数个管芯的金属垫之上以覆盖住该金属垫；
形成一第一介电层于该第一光阻图案与该多数个管芯之上；
烘烤该第一介电层；
去除该第一光阻层；
切割该晶圆上的该多数个管芯以形成个别的管芯；
选取良好的该管芯并附着该管芯到一绝缘基板之上；
烘烤该绝缘基板；
形成一材料层于该绝缘基板之上，其是在该绝缘基板之上的该多数个管芯之间填满该材料层；
烘烤该材料层；
形成一第二介电层于该材料层与该金属垫之上；
蚀刻该金属垫之上的该第二介电层的部分区域以形成第一开口于该金属垫之上；
烘烤该第二介电层；
形成一接触导电层于该第一开口之上以分别与该金属垫作电性耦合；
形成一第二光阻层于该第二介电层与该接触导电层之上；
去除该第二光阻层的一部分区域以形成一第二光阻图案并且暴露该接触导电层以形成第二开口；
形成导线层于该第二光阻图案与该第二开口之上，使得该导线层分别与该接触导电层耦合；
去除剩余的该第二光阻层；
形成一绝缘层于该导线层与该第二介电层之上；
去除该导线层上的该绝缘层的一部分区域以形成第三开口；
烘烤该绝缘层；以及
焊接焊接球于该第三开口之上。
8.如权利要求7所述的晶圆级封装结构的形成方法，其特征在于：包括一于焊接该焊接球步骤之后切割该绝缘基板以绝缘该多数个管芯的步骤；包括一于该去除剩余的该第一光阻层步骤之后背磨该晶圆以得到一厚度约100～300微米的该晶圆的步骤；更包括一形成一环氧化物层于该绝缘基板的背表面的步骤；其中该多数个管芯包括至少二种型态的管芯；其中该第一介电层的材质是旋涂式二氧化硅；其中该绝缘基板的材质是玻璃、硅、陶瓷或石英晶体；其中该材料层的材质是硅胶、环氧化物层、树脂、BCB、聚乙醯、BT、SINR；其中该第二介电层的材质是SINR、BCB、PI；更包括形成一滤光层于该第一介电层之上，该滤光层例如是一红外线滤光层；其中该接触导电层的材质包括钛、铜与其组合；其中该绝缘层的材质包括环氧化物层、树脂与其组合；其中该导线层的材质包括镍、铜、金与其组合；其中该锻烧焊接球的步骤包括：通过由一网印的方法置放该焊接球于该第三开口之上，并且通过由一红外线回流的方法将该焊接球与该导线层的表面连接在一起。
9.一种晶圆级封装结构的形成方法，其特征在于包括：
利用一第一光阻图案形成一第一介电层于一晶圆上的多数个管芯之上；
切割该多数个管芯以形成个别的管芯；
选取良好的该管芯并附着该管芯到一绝缘基板之上；
形成一材料层于该绝缘基板之上，分布于该多数个管芯之间；
形成一第二介电层于该材料层之上；
蚀刻该第二介电层的部分区域以形成第一开口用以曝露该管芯上的金属垫；
形成一导电层于该第一开口之上以分别与该金属垫作电性耦合；
形成一第二光阻图案并暴露该接触导电层以形成第二开口；
形成导线层于该第二光阻图案与该第二开口之上，使得该导线层分别与该接触导电层耦合；
去除该第二光阻图案；
形成一绝缘层于该导线层与该第二介电层之上；
去除该导线层上的该绝缘层的一部分区域以形成第三开口；以及焊接焊接球于该第三开口之上。
10.如权利要求9所述的晶圆级封装结构的形成方法，其特征在于：更包括一于焊接该焊接球步骤之后切割该绝缘基板以绝缘该多数个管芯的步骤；更包括一于该去除该第一光阻图案步骤之后背磨该硅晶圆以得到一厚度100～300微米的该硅晶圆的步骤；包括一形成一环氧化物层于该绝缘基板的背表面的步骤；其中该多数个管芯包括至少二种型态的管芯；其中该第一介电层的材质是旋涂式二氧化硅；其中该绝缘基板的材质是玻璃、硅、陶瓷或石英晶体；其中该材料层的材质是硅胶、环氧化物层、树脂、BCB、PI、BT、SINR；其中该第二介电层的材质是SINR、BCB、PI；更包括形成一滤光层于该第一介电层之上，该滤光层例如是一红外线滤光层；其中该接触导电层的材质包括钛、铜与其组合；其中该绝缘层的材质包括环氧化物层、树脂与其组合；其中该导线层的材质包括镍、铜、金与其组合。
CNB2004100592937A 2004-04-28 2004-06-16 图像感应器模块与晶圆级封装的结构及其形成方法 Expired - Lifetime CN100377361C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/833,345 2004-04-28
US10/833,345 US7061106B2 (en) 2004-04-28 2004-04-28 Structure of image sensor module and a method for manufacturing of wafer level package

Publications (2)

Publication Number Publication Date
CN1691343A CN1691343A (zh) 2005-11-02
CN100377361C true CN100377361C (zh) 2008-03-26

Family

ID=35186207

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100592937A Expired - Lifetime CN100377361C (zh) 2004-04-28 2004-06-16 图像感应器模块与晶圆级封装的结构及其形成方法

Country Status (7)

Country Link
US (3) US7061106B2 (zh)
JP (1) JP2005317887A (zh)
KR (1) KR100600304B1 (zh)
CN (1) CN100377361C (zh)
DE (2) DE102004064028B4 (zh)
SG (1) SG135032A1 (zh)
TW (1) TWI240338B (zh)

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100539234B1 (ko) * 2003-06-11 2005-12-27 삼성전자주식회사 투명 고분자 소재를 적용한 씨모스형 이미지 센서 모듈 및그 제조방법
DE10328265A1 (de) * 2003-06-23 2005-01-27 Infineon Technologies Ag Sensorbauteil und Nutzen zu seiner Herstellung
US7796187B2 (en) * 2004-02-20 2010-09-14 Flextronics Ap Llc Wafer based camera module and method of manufacture
US7872686B2 (en) * 2004-02-20 2011-01-18 Flextronics International Usa, Inc. Integrated lens and chip assembly for a digital camera
TWI253700B (en) * 2004-08-03 2006-04-21 Ind Tech Res Inst Image sensor module packaging structure and method thereof
US7186587B2 (en) * 2004-09-20 2007-03-06 Advanced Semiconductor Engineering Singulation method used in image sensor packaging process and support for use therein
KR100630705B1 (ko) * 2004-10-20 2006-10-02 삼성전자주식회사 카메라 모듈 및 그 제조방법
TWM264775U (en) * 2004-10-21 2005-05-11 Chipmos Technologies Inc Image sensor with multi chip module
US7279782B2 (en) * 2005-01-05 2007-10-09 Advanced Chip Engineering Technology Inc. FBGA and COB package structure for image sensor
KR100735492B1 (ko) * 2005-11-23 2007-07-04 삼성전기주식회사 단차부를 갖는 인쇄회로기판을 이용한 카메라 모듈
TWI295081B (en) * 2006-01-12 2008-03-21 Touch Micro System Tech Method for wafer level package and fabricating cap structures
JP2007288755A (ja) * 2006-04-14 2007-11-01 Optopac Co Ltd カメラモジュール
US20070264424A1 (en) * 2006-05-12 2007-11-15 Nanoopto Corporation Lens arrays and methods of making the same
US8092102B2 (en) 2006-05-31 2012-01-10 Flextronics Ap Llc Camera module with premolded lens housing and method of manufacture
US7498646B2 (en) * 2006-07-19 2009-03-03 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
FR2904144A1 (fr) * 2006-07-19 2008-01-25 St Microelectronics Rousset Procede de fabrication d'un wafer de semi-conducteur comprenant un filtre optique integre
KR101176545B1 (ko) * 2006-07-26 2012-08-28 삼성전자주식회사 마이크로 렌즈의 형성방법과 마이크로 렌즈를 포함한이미지 센서 및 그의 제조방법
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
US7459729B2 (en) * 2006-12-29 2008-12-02 Advanced Chip Engineering Technology, Inc. Semiconductor image device package with die receiving through-hole and method of the same
US7566854B2 (en) * 2006-12-08 2009-07-28 Advanced Chip Engineering Technology Inc. Image sensor module
US20080136012A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Imagine sensor package and forming method of the same
US8110906B2 (en) 2007-01-23 2012-02-07 Infineon Technologies Ag Semiconductor device including isolation layer
US7923823B2 (en) 2007-01-23 2011-04-12 Infineon Technologies Ag Semiconductor device with parylene coating
US20080197435A1 (en) * 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Wafer level image sensor package with die receiving cavity and method of making the same
US20080211080A1 (en) * 2007-03-01 2008-09-04 Advanced Chip Engineering Technology Inc. Package structure to improve the reliability for WLP
US8093092B2 (en) * 2007-06-08 2012-01-10 Flextronics Ap, Llc Techniques for glass attachment in an image sensor package
TWI332790B (en) * 2007-06-13 2010-11-01 Ind Tech Res Inst Image sensor module with a three-dimensional dies-stacking structure
US20090032925A1 (en) * 2007-07-31 2009-02-05 England Luke G Packaging with a connection structure
TWI360207B (en) * 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US8488046B2 (en) * 2007-12-27 2013-07-16 Digitaloptics Corporation Configurable tele wide module
US20090206431A1 (en) * 2008-02-20 2009-08-20 Micron Technology, Inc. Imager wafer level module and method of fabrication and use
TWI384916B (zh) * 2008-03-25 2013-02-01 Bruce C S Chou 具軟性電路板之微結構及其製造方法
US8048708B2 (en) * 2008-06-25 2011-11-01 Micron Technology, Inc. Method and apparatus providing an imager module with a permanent carrier
US8193632B2 (en) * 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
TWI387087B (zh) * 2008-08-06 2013-02-21 Ind Tech Res Inst 立體導通結構及其製造方法
US8791470B2 (en) 2009-10-05 2014-07-29 Zena Technologies, Inc. Nano structured LEDs
US8890271B2 (en) 2010-06-30 2014-11-18 Zena Technologies, Inc. Silicon nitride light pipes for image sensors
US9299866B2 (en) 2010-12-30 2016-03-29 Zena Technologies, Inc. Nanowire array based solar energy harvesting device
US8866065B2 (en) 2010-12-13 2014-10-21 Zena Technologies, Inc. Nanowire arrays comprising fluorescent nanowires
US8274039B2 (en) 2008-11-13 2012-09-25 Zena Technologies, Inc. Vertical waveguides with various functionality on integrated circuits
US9000353B2 (en) 2010-06-22 2015-04-07 President And Fellows Of Harvard College Light absorption and filtering properties of vertically oriented semiconductor nano wires
US9478685B2 (en) 2014-06-23 2016-10-25 Zena Technologies, Inc. Vertical pillar structured infrared detector and fabrication method for the same
US8546742B2 (en) 2009-06-04 2013-10-01 Zena Technologies, Inc. Array of nanowires in a single cavity with anti-reflective coating on substrate
US8748799B2 (en) 2010-12-14 2014-06-10 Zena Technologies, Inc. Full color single pixel including doublet or quadruplet si nanowires for image sensors
US9343490B2 (en) 2013-08-09 2016-05-17 Zena Technologies, Inc. Nanowire structured color filter arrays and fabrication method of the same
US9406709B2 (en) 2010-06-22 2016-08-02 President And Fellows Of Harvard College Methods for fabricating and using nanowires
US8519379B2 (en) 2009-12-08 2013-08-27 Zena Technologies, Inc. Nanowire structured photodiode with a surrounding epitaxially grown P or N layer
US8735797B2 (en) 2009-12-08 2014-05-27 Zena Technologies, Inc. Nanowire photo-detector grown on a back-side illuminated image sensor
US8229255B2 (en) * 2008-09-04 2012-07-24 Zena Technologies, Inc. Optical waveguides in image sensors
US8299472B2 (en) 2009-12-08 2012-10-30 Young-June Yu Active pixel sensor with nanowire structured photodetectors
US8269985B2 (en) 2009-05-26 2012-09-18 Zena Technologies, Inc. Determination of optimal diameters for nanowires
US8835831B2 (en) 2010-06-22 2014-09-16 Zena Technologies, Inc. Polarized light detecting device and fabrication methods of the same
US9515218B2 (en) 2008-09-04 2016-12-06 Zena Technologies, Inc. Vertical pillar structured photovoltaic devices with mirrors and optical claddings
US9082673B2 (en) 2009-10-05 2015-07-14 Zena Technologies, Inc. Passivated upstanding nanostructures and methods of making the same
US8889455B2 (en) 2009-12-08 2014-11-18 Zena Technologies, Inc. Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor
US8232633B2 (en) * 2008-09-25 2012-07-31 King Dragon International Inc. Image sensor package with dual substrates and the method of the same
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
TWI466259B (zh) * 2009-07-21 2014-12-21 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI508273B (zh) * 2010-03-19 2015-11-11 Xintec Inc 影像感測元件封裝構件及其製作方法
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US20110294237A1 (en) * 2010-05-27 2011-12-01 MOS Art Pack Corporation Packaging method of semiconductor device
TWI405279B (zh) * 2010-07-23 2013-08-11 Global Unichip Corp Packaging of semiconductor components
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9324755B2 (en) * 2014-05-05 2016-04-26 Semiconductor Components Industries, Llc Image sensors with reduced stack height
US10032725B2 (en) * 2015-02-26 2018-07-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN105023900A (zh) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 埋入硅基板扇出型封装结构及其制造方法
KR102619666B1 (ko) 2016-11-23 2023-12-29 삼성전자주식회사 이미지 센서 패키지
CN107396239B (zh) * 2017-06-06 2023-08-15 纽威仕微电子（无锡）有限公司 一种水听器及其封装工艺
US10267988B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Photonic package and method forming same
DE102017124815B4 (de) * 2017-06-30 2019-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Photonisches Package und Verfahren zu dessen Bildung
US10319768B2 (en) * 2017-08-28 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor scheme for optical and electrical improvement
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
US11075242B2 (en) 2017-11-27 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices for image sensing
US20190181116A1 (en) * 2017-12-11 2019-06-13 Semiconductor Components Industries, Llc Fan-out structure for semiconductor packages and related methods
KR102052804B1 (ko) 2017-12-15 2019-12-05 삼성전기주식회사 팬-아웃 센서 패키지
KR102016495B1 (ko) 2018-01-31 2019-10-21 삼성전기주식회사 팬-아웃 센서 패키지
JP7389029B2 (ja) * 2018-06-29 2023-11-29 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、電子機器、および固体撮像装置の製造方法
US10861895B2 (en) * 2018-11-20 2020-12-08 Ningbo Semiconductor International Corporation Image capturing assembly and packaging method thereof, lens module and electronic device
WO2020115813A1 (ja) 2018-12-04 2020-06-11 オリンパス株式会社 半導体装置、内視鏡、および、半導体装置の製造方法
CN113572445B (zh) * 2021-09-23 2022-01-07 深圳新声半导体有限公司 滤波器芯片封装结构及用于滤波器芯片封装的方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055761A (en) * 1975-03-14 1977-10-25 Nippon Kogaku K.K. Light receiving device for photoelectric conversion element
US6297071B1 (en) * 1998-07-22 2001-10-02 Eastman Kodak Company Method of making planar image sensor color filter arrays
US6414299B1 (en) * 1999-02-17 2002-07-02 Canon Kabushiki Kaisha Method of mounting optical sensor package
CN1395313A (zh) * 2001-07-06 2003-02-05 联华电子股份有限公司 互补式金氧半图像感测器的结构及其制造方法
US6518656B1 (en) * 1999-10-19 2003-02-11 Sony Corporation Reduced thickness optical image pickup device with improved sealing and method of making same
US20030057359A1 (en) * 1999-12-08 2003-03-27 Steven Webster Image sensor package having optical element
US6599770B2 (en) * 2000-10-19 2003-07-29 Shinko Electric Industries, Co., Ltd. Process for manufacturing an optical device
US20040041938A1 (en) * 2002-08-28 2004-03-04 Samsung Electro-Mechanics Co., Ltd. Embedded type camera module

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171883B1 (en) * 1999-02-18 2001-01-09 Taiwan Semiconductor Manufacturing Company Image array optoelectronic microelectronic fabrication with enhanced optical stability and method for fabrication thereof
US6483030B1 (en) * 1999-12-08 2002-11-19 Amkor Technology, Inc. Snap lid image sensor package
JP2001313350A (ja) * 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
JP2002299546A (ja) * 2001-04-04 2002-10-11 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
TW558064U (en) * 2002-09-23 2003-10-11 Ist Internat Semiconductor Tec Thin type camera module
US6808960B2 (en) * 2002-10-25 2004-10-26 Omni Vision International Holding Ltd Method for making and packaging image sensor die using protective coating
US20040150740A1 (en) * 2003-01-30 2004-08-05 Hsin Chung Hsien Miniaturized image sensor module
JP2004242166A (ja) * 2003-02-07 2004-08-26 Seiko Epson Corp 光モジュール及びその製造方法並びに電子機器
JP4510403B2 (ja) * 2003-05-08 2010-07-21 富士フイルム株式会社 カメラモジュール及びカメラモジュールの製造方法
US7253397B2 (en) * 2004-02-23 2007-08-07 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050236684A1 (en) * 2004-04-27 2005-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor packaging structure and method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055761A (en) * 1975-03-14 1977-10-25 Nippon Kogaku K.K. Light receiving device for photoelectric conversion element
US6297071B1 (en) * 1998-07-22 2001-10-02 Eastman Kodak Company Method of making planar image sensor color filter arrays
US6414299B1 (en) * 1999-02-17 2002-07-02 Canon Kabushiki Kaisha Method of mounting optical sensor package
US6518656B1 (en) * 1999-10-19 2003-02-11 Sony Corporation Reduced thickness optical image pickup device with improved sealing and method of making same
US20030057359A1 (en) * 1999-12-08 2003-03-27 Steven Webster Image sensor package having optical element
US6599770B2 (en) * 2000-10-19 2003-07-29 Shinko Electric Industries, Co., Ltd. Process for manufacturing an optical device
CN1395313A (zh) * 2001-07-06 2003-02-05 联华电子股份有限公司 互补式金氧半图像感测器的结构及其制造方法
US20040041938A1 (en) * 2002-08-28 2004-03-04 Samsung Electro-Mechanics Co., Ltd. Embedded type camera module

Also Published As

Publication number Publication date
US7061106B2 (en) 2006-06-13
DE102004064028B4 (de) 2009-04-02
US7525139B2 (en) 2009-04-28
DE102004034397B4 (de) 2006-11-16
US20050242408A1 (en) 2005-11-03
TWI240338B (en) 2005-09-21
TW200536025A (en) 2005-11-01
SG135032A1 (en) 2007-09-28
JP2005317887A (ja) 2005-11-10
KR100600304B1 (ko) 2006-07-13
CN1691343A (zh) 2005-11-02
KR20050105424A (ko) 2005-11-04
US20050242409A1 (en) 2005-11-03
US20080108168A1 (en) 2008-05-08
DE102004034397A1 (de) 2005-12-01
US7501310B2 (en) 2009-03-10

Similar Documents

Publication Publication Date Title
CN100377361C (zh) 图像感应器模块与晶圆级封装的结构及其形成方法
TWI278121B (en) FBGA and COB package structure for image sensor
US10913655B2 (en) Manufacturing of integrated circuit resonator
CN100470742C (zh) 芯片尺寸封装的结构与其形成方法
CN1324667C (zh) 扩散式晶圆型态封装的结构与其形成方法
CN1901161B (zh) 连续电镀制作线路组件的方法及线路组件结构
US8703518B2 (en) Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7514767B2 (en) Fan out type wafer level package structure and method of the same
US11764239B2 (en) Wafer level image sensor package
US7884015B2 (en) Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
TW200807702A (en) Structure of image sensor module and a method for manufacturing of wafer level package
CN100524725C (zh) 半导体装置及其制造方法
US10490595B2 (en) Image sensor chip scale packages and related methods
TW200849507A (en) CMOS image sensor chip scale package with die receiving through-hole and method of the same
CN103681702A (zh) 用于传感器模块的方法和装置
CN101246897A (zh) 具有晶粒容纳孔洞的晶圆级影像传感器封装与其方法
JP2008228308A (ja) ビルドインパッケージキャビティを有するイメージセンサモジュールおよびその方法
KR20090004707A (ko) 제거가능한 보호 필름을 이용한 이미지 센서 패키지 및 그제조 방법
CN104054164A (zh) 半导体装置及其制造方法
JP2008205429A (ja) イメージセンサパッケージおよびその形成方法
JP2004179495A (ja) 半導体装置
US20090267172A1 (en) Method of manufacturing an image sensing micromodule
TWI251931B (en) Imagine sensor with a protection layer
TW200814758A (en) Structure of image sensor module and a method for manufacturing of wafer level package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee after: Quncheng Energy Co.,Ltd.

Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee before: ADL Engineering Inc.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20231017

Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee after: ADL Engineering Inc.

Address before: Hsinchu County, Taiwan, China

Patentee before: Advanced Chip Engineering Technology Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240108

Address after: No. 8, Lixing 6th Road, Hsinchu City, Science Industrial Park, Hsinchu City, Taiwan, China, China

Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd.

Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee before: Quncheng Energy Co.,Ltd.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20080326

CX01 Expiry of patent term