CN100375097C - 个体化方法及系统 - Google Patents
个体化方法及系统 Download PDFInfo
- Publication number
- CN100375097C CN100375097C CNB00818531XA CN00818531A CN100375097C CN 100375097 C CN100375097 C CN 100375097C CN B00818531X A CNB00818531X A CN B00818531XA CN 00818531 A CN00818531 A CN 00818531A CN 100375097 C CN100375097 C CN 100375097C
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- Prior art keywords
- circuit
- electrical characteristics
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- individuation
- deterministic process
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17708700P | 2000-01-20 | 2000-01-20 | |
US60/177,087 | 2000-01-20 | ||
US18975600P | 2000-03-16 | 2000-03-16 | |
US60/189,756 | 2000-03-16 | ||
US19120800P | 2000-03-22 | 2000-03-22 | |
US60/191,208 | 2000-03-22 | ||
US23745800P | 2000-10-02 | 2000-10-02 | |
US60/237,458 | 2000-10-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1425197A CN1425197A (zh) | 2003-06-18 |
CN100375097C true CN100375097C (zh) | 2008-03-12 |
Family
ID=27497219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB00818531XA Expired - Fee Related CN100375097C (zh) | 2000-01-20 | 2000-12-18 | 个体化方法及系统 |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1249042A1 (fr) |
JP (1) | JP2003520451A (fr) |
KR (2) | KR100859829B1 (fr) |
CN (1) | CN100375097C (fr) |
AU (1) | AU2001223813A1 (fr) |
IL (2) | IL150784A0 (fr) |
WO (1) | WO2001054194A1 (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10162307A1 (de) * | 2001-12-19 | 2003-07-03 | Philips Intellectual Property | Verfahren und Anordnung zur Herstellung von maskenprogrammierten ROMs unter Verwendung einer mehrere Systeme umfassenden Maske sowie ein entsprechendes Computerprogrammprodukt und ein entsprechendes computerlesbares Speichermedium |
DE10319976A1 (de) * | 2003-05-05 | 2004-12-09 | Infineon Technologies Ag | Individualisierter Halbleiterchip und Verfahren zur Individualisierung von Halbleiterchips |
CN1922727B (zh) * | 2004-02-20 | 2011-12-21 | 株式会社半导体能源研究所 | 半导体器件及ic卡、ic标签、rfid、转发器、票据、证券、护照、电子装置、包和外衣的制造方法 |
GB0410975D0 (en) | 2004-05-17 | 2004-06-16 | Nds Ltd | Chip shielding system and method |
JP5400279B2 (ja) | 2007-06-07 | 2014-01-29 | スパンション エルエルシー | 半導体装置及びその製造方法並びに半導体製造装置 |
JP5761947B2 (ja) | 2010-09-02 | 2015-08-12 | キヤノン株式会社 | 半導体集積回路装置 |
CN102509726A (zh) * | 2011-11-14 | 2012-06-20 | 上海宏力半导体制造有限公司 | 具有加密结构的ip模块及其制造方法 |
US9672316B2 (en) | 2013-07-17 | 2017-06-06 | Arm Limited | Integrated circuit manufacture using direct write lithography |
TWI714419B (zh) * | 2020-01-06 | 2020-12-21 | 力晶積成電子製造股份有限公司 | 具有隱藏的識別碼的半導體堆疊結構 |
DE102022110501A1 (de) | 2022-04-29 | 2023-11-02 | Infineon Technologies Ag | Identifikationscodes auf halbleiterchips |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5302491A (en) * | 1989-12-20 | 1994-04-12 | North American Philips Corporation | Method of encoding identification information on circuit dice using step and repeat lithography |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4409686A (en) | 1980-06-16 | 1983-10-11 | Harris Corporation | Method of serialization of dice |
US4510673A (en) | 1983-06-23 | 1985-04-16 | International Business Machines Corporation | Laser written chip identification method |
JPH01293616A (ja) * | 1988-05-23 | 1989-11-27 | Nec Corp | 半導体集積回路の製造方法 |
JPH0247825A (ja) * | 1988-08-10 | 1990-02-16 | Mitsubishi Electric Corp | 荷電ビーム描画データ作成方法 |
DE69021549T2 (de) * | 1989-10-13 | 1996-04-18 | Foxboro Co | Anwendungsorientiertes automatisiertes bandbonding. |
EP0434141B1 (fr) * | 1989-12-20 | 1998-11-04 | Koninklijke Philips Electronics N.V. | Méthode de codage d'informations visant à identifier des éléments de circuit en utilisant la lithographie pas à pas |
US5208178A (en) * | 1990-08-02 | 1993-05-04 | Hitachi, Ltd. | Manufacturing a semiconductor integrated circuit device having on chip logic correction |
JPH07123101B2 (ja) * | 1990-09-14 | 1995-12-25 | 株式会社東芝 | 半導体装置 |
JP2913817B2 (ja) * | 1990-10-30 | 1999-06-28 | 日本電気株式会社 | 半導体メモリの製造方法 |
-
2000
- 2000-12-18 WO PCT/GB2000/004869 patent/WO2001054194A1/fr active Application Filing
- 2000-12-18 IL IL15078400A patent/IL150784A0/xx not_active IP Right Cessation
- 2000-12-18 JP JP2001553584A patent/JP2003520451A/ja active Pending
- 2000-12-18 KR KR1020087006747A patent/KR100859829B1/ko not_active IP Right Cessation
- 2000-12-18 CN CNB00818531XA patent/CN100375097C/zh not_active Expired - Fee Related
- 2000-12-18 AU AU2001223813A patent/AU2001223813A1/en not_active Abandoned
- 2000-12-18 KR KR1020027009346A patent/KR100859825B1/ko not_active IP Right Cessation
- 2000-12-18 EP EP00987564A patent/EP1249042A1/fr active Pending
-
2002
- 2002-07-17 IL IL150784A patent/IL150784A/en unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5302491A (en) * | 1989-12-20 | 1994-04-12 | North American Philips Corporation | Method of encoding identification information on circuit dice using step and repeat lithography |
Also Published As
Publication number | Publication date |
---|---|
IL150784A (en) | 2007-05-15 |
WO2001054194A1 (fr) | 2001-07-26 |
KR100859829B1 (ko) | 2008-09-23 |
CN1425197A (zh) | 2003-06-18 |
EP1249042A1 (fr) | 2002-10-16 |
KR20080033547A (ko) | 2008-04-16 |
KR20020086474A (ko) | 2002-11-18 |
AU2001223813A1 (en) | 2001-07-31 |
IL150784A0 (en) | 2003-02-12 |
KR100859825B1 (ko) | 2008-09-23 |
JP2003520451A (ja) | 2003-07-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080312 Termination date: 20101218 |