CH653482A5 - Verfahren zur herstellung einer integrierten schaltung mit einem feldeffekttransistor und durch ein derartiges verfahren hergestellte schaltung. - Google Patents

Verfahren zur herstellung einer integrierten schaltung mit einem feldeffekttransistor und durch ein derartiges verfahren hergestellte schaltung. Download PDF

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Publication number
CH653482A5
CH653482A5 CH3064/80A CH306480A CH653482A5 CH 653482 A5 CH653482 A5 CH 653482A5 CH 3064/80 A CH3064/80 A CH 3064/80A CH 306480 A CH306480 A CH 306480A CH 653482 A5 CH653482 A5 CH 653482A5
Authority
CH
Switzerland
Prior art keywords
zones
mask
semiconductor body
source
layer
Prior art date
Application number
CH3064/80A
Other languages
German (de)
English (en)
Inventor
Pieter Johannes Wilhel Jochems
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH653482A5 publication Critical patent/CH653482A5/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CH3064/80A 1979-04-23 1980-04-21 Verfahren zur herstellung einer integrierten schaltung mit einem feldeffekttransistor und durch ein derartiges verfahren hergestellte schaltung. CH653482A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7903158A NL7903158A (nl) 1979-04-23 1979-04-23 Werkwijze voor het vervaardigen van een veldeffekt- transistor met geisoleerde poortelektrode, en transistor vervaardigd door toepassing van een derge- lijke werkwijze.

Publications (1)

Publication Number Publication Date
CH653482A5 true CH653482A5 (de) 1985-12-31

Family

ID=19833027

Family Applications (1)

Application Number Title Priority Date Filing Date
CH3064/80A CH653482A5 (de) 1979-04-23 1980-04-21 Verfahren zur herstellung einer integrierten schaltung mit einem feldeffekttransistor und durch ein derartiges verfahren hergestellte schaltung.

Country Status (10)

Country Link
US (1) US4343079A (en, 2012)
JP (1) JPS55141758A (en, 2012)
AU (1) AU537858B2 (en, 2012)
CA (1) CA1146675A (en, 2012)
CH (1) CH653482A5 (en, 2012)
DE (1) DE3015101A1 (en, 2012)
FR (1) FR2455361A1 (en, 2012)
GB (1) GB2047961B (en, 2012)
IT (1) IT1140878B (en, 2012)
NL (1) NL7903158A (en, 2012)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
US5252505A (en) * 1979-05-25 1993-10-12 Hitachi, Ltd. Method for manufacturing a semiconductor device
JPS60106142A (ja) * 1983-11-15 1985-06-11 Nec Corp 半導体素子の製造方法
US4675982A (en) * 1985-10-31 1987-06-30 International Business Machines Corporation Method of making self-aligned recessed oxide isolation regions
EP0585601B1 (en) 1992-07-31 1999-04-28 Hughes Electronics Corporation Integrated circuit security system and method with implanted interconnections
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
JPS5528229B1 (en, 2012) * 1971-03-19 1980-07-26
FR2134290B1 (en, 2012) * 1971-04-30 1977-03-18 Texas Instruments France
NL7113561A (en, 2012) * 1971-10-02 1973-04-04
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
JPS52131483A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device
NL185376C (nl) * 1976-10-25 1990-03-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
JPS53123678A (en) * 1977-04-04 1978-10-28 Nec Corp Manufacture of field effect semiconductor device of insulation gate type
JPS53123661A (en) * 1977-04-04 1978-10-28 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS53144280A (en) * 1977-05-23 1978-12-15 Hitachi Ltd Mis semiconductor device
US4268950A (en) * 1978-06-05 1981-05-26 Texas Instruments Incorporated Post-metal ion implant programmable MOS read only memory
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
AU537858B2 (en) 1984-07-19
JPS55141758A (en) 1980-11-05
FR2455361B1 (en, 2012) 1983-04-29
AU5765180A (en) 1980-10-30
DE3015101A1 (de) 1980-11-06
NL7903158A (nl) 1980-10-27
GB2047961B (en) 1983-08-03
GB2047961A (en) 1980-12-03
IT1140878B (it) 1986-10-10
FR2455361A1 (fr) 1980-11-21
IT8021514A0 (it) 1980-04-18
DE3015101C2 (en, 2012) 1990-03-29
CA1146675A (en) 1983-05-17
US4343079A (en) 1982-08-10

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PL Patent ceased
PL Patent ceased