CA2109687A1 - Methode de placage pour la realisation de traces metalliques - Google Patents

Methode de placage pour la realisation de traces metalliques

Info

Publication number
CA2109687A1
CA2109687A1 CA002109687A CA2109687A CA2109687A1 CA 2109687 A1 CA2109687 A1 CA 2109687A1 CA 002109687 A CA002109687 A CA 002109687A CA 2109687 A CA2109687 A CA 2109687A CA 2109687 A1 CA2109687 A1 CA 2109687A1
Authority
CA
Canada
Prior art keywords
conductor
electrical connections
preworked
foils
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002109687A
Other languages
English (en)
Inventor
Walter Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dyconex Patente AG
Original Assignee
Dyconex Patente AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dyconex Patente AG filed Critical Dyconex Patente AG
Priority to CA002109687A priority Critical patent/CA2109687A1/fr
Priority to EP94100505A priority patent/EP0608726B1/fr
Priority to DE59402178T priority patent/DE59402178D1/de
Priority to JP6022060A priority patent/JPH07111375A/ja
Priority to US08/187,393 priority patent/US5457881A/en
Publication of CA2109687A1 publication Critical patent/CA2109687A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4635Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0394Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/044Solder dip coating, i.e. coating printed conductors, e.g. pads by dipping in molten solder or by wave soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189Pressing leads, bumps or a die through an insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
CA002109687A 1993-01-26 1993-11-22 Methode de placage pour la realisation de traces metalliques Abandoned CA2109687A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002109687A CA2109687A1 (fr) 1993-01-26 1993-11-22 Methode de placage pour la realisation de traces metalliques
EP94100505A EP0608726B1 (fr) 1993-01-26 1994-01-14 Procédé pour le placage de connexions traversantes entre des feuilles conductrices
DE59402178T DE59402178D1 (de) 1993-01-26 1994-01-14 Verfahren zum Durchplattieren von Leiterfolien
JP6022060A JPH07111375A (ja) 1993-01-26 1994-01-21 多層プリント回路基板およびその製造方法ならびに多層プリント回路基板の導体箔
US08/187,393 US5457881A (en) 1993-01-26 1994-01-25 Method for the through plating of conductor foils

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH21793 1993-01-26
CA002109687A CA2109687A1 (fr) 1993-01-26 1993-11-22 Methode de placage pour la realisation de traces metalliques

Publications (1)

Publication Number Publication Date
CA2109687A1 true CA2109687A1 (fr) 1995-05-23

Family

ID=25676807

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002109687A Abandoned CA2109687A1 (fr) 1993-01-26 1993-11-22 Methode de placage pour la realisation de traces metalliques

Country Status (5)

Country Link
US (1) US5457881A (fr)
EP (1) EP0608726B1 (fr)
JP (1) JPH07111375A (fr)
CA (1) CA2109687A1 (fr)
DE (1) DE59402178D1 (fr)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3457348B2 (ja) 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
US5600103A (en) * 1993-04-16 1997-02-04 Kabushiki Kaisha Toshiba Circuit devices and fabrication method of the same
DE69419219T2 (de) * 1993-09-03 2000-01-05 Kabushiki Kaisha Toshiba, Kawasaki Leiterplatte und Verfahren zur Herstellung solcher Leiterplatten
DE9407103U1 (de) * 1994-04-28 1994-09-08 Andus Electronic GmbH Leiterplattentechnik, 10997 Berlin Verbindungsanordnung für Multilayer-Schaltungen
CN1099158C (zh) * 1994-05-02 2003-01-15 埃普科斯股份有限公司 电子部件的封闭装置
JP3474937B2 (ja) * 1994-10-07 2003-12-08 株式会社東芝 実装用配線板の製造方法、半導体パッケージの製造方法
JP2768918B2 (ja) * 1995-07-18 1998-06-25 山一電機株式会社 配線基板における配線パターン間接続構造
EP0805614B1 (fr) * 1995-11-17 2005-04-13 Kabushiki Kaisha Toshiba Tableau de connexion multicouches, materiau prefabrique pour ce tableau, procede de fabrication de ce dernier groupement de composants electroniques et procede de formation de connexions verticales conductrices
US5839188A (en) 1996-01-05 1998-11-24 Alliedsignal Inc. Method of manufacturing a printed circuit assembly
US6147870A (en) * 1996-01-05 2000-11-14 Honeywell International Inc. Printed circuit assembly having locally enhanced wiring density
DE19618100A1 (de) * 1996-05-06 1997-11-13 Siemens Ag Verfahren zur Herstellung einer Mehrlagen-Verbundstruktur mit elektrisch leitenden Verbindungen
GB9610689D0 (en) * 1996-05-22 1996-07-31 Int Computers Ltd Flip chip attachment
JP3687041B2 (ja) * 1997-04-16 2005-08-24 大日本印刷株式会社 配線基板、配線基板の製造方法、および半導体パッケージ
WO1998056220A1 (fr) * 1997-06-06 1998-12-10 Ibiden Co., Ltd. Plaquette de circuit simple face et procede de fabrication de ladite plaquette
US6162365A (en) * 1998-03-04 2000-12-19 International Business Machines Corporation Pd etch mask for copper circuitization
JP3197540B2 (ja) * 1999-02-05 2001-08-13 ソニーケミカル株式会社 基板素片、及びフレキシブル基板
JP3183653B2 (ja) * 1999-08-26 2001-07-09 ソニーケミカル株式会社 フレキシブル基板
TW512467B (en) * 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
EP1194023A4 (fr) * 1999-12-14 2005-11-09 Matsushita Electric Ind Co Ltd Carte a circuit imprime multicouche et procede de production
JP2001345549A (ja) * 2000-06-01 2001-12-14 Fujitsu Ltd 実装用基板の製造方法及び部品実装方法並びに実装用基板製造装置
JP4322402B2 (ja) * 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
US6815709B2 (en) * 2001-05-23 2004-11-09 International Business Machines Corporation Structure having flush circuitry features and method of making
KR100671541B1 (ko) * 2001-06-21 2007-01-18 (주)글로벌써키트 함침 인쇄회로기판 제조방법
EP1525630A2 (fr) * 2002-07-29 2005-04-27 Siemens Aktiengesellschaft Composant electronique comprenant des materiaux fonctionnels majoritairement organiques et procede pour le produire
JP3902752B2 (ja) * 2002-10-01 2007-04-11 日本メクトロン株式会社 多層回路基板
JP2004186307A (ja) 2002-12-02 2004-07-02 Tdk Corp 電子部品の製造方法および、電子部品
JP4597686B2 (ja) * 2004-02-24 2010-12-15 日本メクトロン株式会社 多層フレキシブル回路基板の製造方法
JP2006156669A (ja) * 2004-11-29 2006-06-15 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
KR100723270B1 (ko) 2005-12-13 2007-05-30 전자부품연구원 다층 인쇄회로기판 제조방법
US7631423B2 (en) * 2006-02-13 2009-12-15 Sanmina-Sci Corporation Method and process for embedding electrically conductive elements in a dielectric layer
CN103360976B (zh) * 2006-04-26 2016-08-03 日立化成株式会社 粘接带及使用其的太阳能电池模块
DE112008000704T5 (de) * 2007-03-22 2010-04-29 Murata Mfg. Co., Ltd., Nagaokakyo-shi Kontaktlochbildungsverfahren, das ein elektrophotographisches Druckverfahren verwendet
JP5143266B1 (ja) 2011-09-30 2013-02-13 株式会社東芝 フレキシブルプリント配線板の製造装置および製造方法
US9282646B2 (en) 2012-05-24 2016-03-08 Unimicron Technology Corp. Interposed substrate and manufacturing method thereof
TWI637467B (zh) 2012-05-24 2018-10-01 欣興電子股份有限公司 中介基材及其製作方法
CN103456715B (zh) * 2012-06-04 2017-06-09 欣兴电子股份有限公司 中介基材及其制作方法
CN103517558B (zh) * 2012-06-20 2017-03-22 碁鼎科技秦皇岛有限公司 封装基板制作方法
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates

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GB1126370A (en) * 1965-12-29 1968-09-05 British Aircraft Corp Ltd Improvements relating to printed circuits
GB1353671A (en) * 1971-06-10 1974-05-22 Int Computers Ltd Methods of forming circuit interconnections
US3953924A (en) * 1975-06-30 1976-05-04 Rockwell International Corporation Process for making a multilayer interconnect system
US4769309A (en) * 1986-10-21 1988-09-06 Westinghouse Electric Corp. Printed circuit boards and method for manufacturing printed circuit boards
US5072075A (en) * 1989-06-28 1991-12-10 Digital Equipment Corporation Double-sided hybrid high density circuit board and method of making same
US4991285A (en) * 1989-11-17 1991-02-12 Rockwell International Corporation Method of fabricating multi-layer board
JPH04278598A (ja) * 1991-03-07 1992-10-05 Nec Corp 多層印刷配線板の製造方法
DE9102817U1 (de) * 1991-03-07 1991-09-05 Andus Electronic GmbH Leiterplattentechnik, 10997 Berlin Innenliegende Verbindung zum Aufbau von Multilayerschaltungen
US5374469A (en) * 1991-09-19 1994-12-20 Nitto Denko Corporation Flexible printed substrate
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing

Also Published As

Publication number Publication date
EP0608726B1 (fr) 1997-03-26
US5457881A (en) 1995-10-17
EP0608726A1 (fr) 1994-08-03
JPH07111375A (ja) 1995-04-25
DE59402178D1 (de) 1997-04-30

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Legal Events

Date Code Title Description
FZDE Discontinued