DE9407103U1 - Verbindungsanordnung für Multilayer-Schaltungen - Google Patents

Verbindungsanordnung für Multilayer-Schaltungen

Info

Publication number
DE9407103U1
DE9407103U1 DE19949407103 DE9407103U DE9407103U1 DE 9407103 U1 DE9407103 U1 DE 9407103U1 DE 19949407103 DE19949407103 DE 19949407103 DE 9407103 U DE9407103 U DE 9407103U DE 9407103 U1 DE9407103 U1 DE 9407103U1
Authority
DE
Germany
Prior art keywords
connection arrangement
multilayer circuits
multilayer
circuits
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19949407103
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Andus Electronic Leiterpl GmbH
Original Assignee
Andus Electronic Leiterpl GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Andus Electronic Leiterpl GmbH filed Critical Andus Electronic Leiterpl GmbH
Priority to DE19949407103 priority Critical patent/DE9407103U1/de
Publication of DE9407103U1 publication Critical patent/DE9407103U1/de
Priority to DE19515159A priority patent/DE19515159A1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE19949407103 1994-04-28 1994-04-28 Verbindungsanordnung für Multilayer-Schaltungen Expired - Lifetime DE9407103U1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19949407103 DE9407103U1 (de) 1994-04-28 1994-04-28 Verbindungsanordnung für Multilayer-Schaltungen
DE19515159A DE19515159A1 (de) 1994-04-28 1995-04-25 Verbindungsanordnung und Verfahren zur Herstellung einer Verbindungsanordnung für Multilayer-Schaltungen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19949407103 DE9407103U1 (de) 1994-04-28 1994-04-28 Verbindungsanordnung für Multilayer-Schaltungen

Publications (1)

Publication Number Publication Date
DE9407103U1 true DE9407103U1 (de) 1994-09-08

Family

ID=6907998

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19949407103 Expired - Lifetime DE9407103U1 (de) 1994-04-28 1994-04-28 Verbindungsanordnung für Multilayer-Schaltungen
DE19515159A Withdrawn DE19515159A1 (de) 1994-04-28 1995-04-25 Verbindungsanordnung und Verfahren zur Herstellung einer Verbindungsanordnung für Multilayer-Schaltungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19515159A Withdrawn DE19515159A1 (de) 1994-04-28 1995-04-25 Verbindungsanordnung und Verfahren zur Herstellung einer Verbindungsanordnung für Multilayer-Schaltungen

Country Status (1)

Country Link
DE (2) DE9407103U1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69634597T2 (de) * 1995-11-17 2006-02-09 Kabushiki Kaisha Toshiba, Kawasaki Mehrschichtige leiterplatte, vorgefertigtes material für diese leiterplatte, verfahren zur herstellung einer mehrschichtigen leiterplatte, packung elektronischer bauelemente und verfahren zur herstellung vertikaler, elektrisch leitender verbindungen
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
DE10354118A1 (de) * 2003-11-19 2005-06-02 Ruwel Ag Verfahren zur Herstellung von Leiterplatten und Leiterplatte
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3843528C1 (de) * 1988-12-23 1990-05-23 Schoeller & Co Elektronik Gmbh, 3552 Wetter, De
DE9102817U1 (de) * 1991-03-07 1991-09-05 Andus Electronic Gmbh Leiterplattentechnik, 1000 Berlin, De
CA2109687A1 (en) * 1993-01-26 1995-05-23 Walter Schmidt Method for the through plating of conductor foils
US5600103A (en) * 1993-04-16 1997-02-04 Kabushiki Kaisha Toshiba Circuit devices and fabrication method of the same

Also Published As

Publication number Publication date
DE19515159A1 (de) 1995-11-02

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