CA1267230A - Selective operation of processing elements in a single instruction, multiple stream (simd) computer system - Google Patents

Selective operation of processing elements in a single instruction, multiple stream (simd) computer system

Info

Publication number
CA1267230A
CA1267230A CA000512328A CA512328A CA1267230A CA 1267230 A CA1267230 A CA 1267230A CA 000512328 A CA000512328 A CA 000512328A CA 512328 A CA512328 A CA 512328A CA 1267230 A CA1267230 A CA 1267230A
Authority
CA
Canada
Prior art keywords
instruction
bus
processors
coupled
processing means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000512328A
Other languages
English (en)
French (fr)
Inventor
Thomas D.S. Duff
Thomas K. Porter
Adam E. Levinthal
Loren C. Carpenter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pixar
Original Assignee
Pixar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pixar filed Critical Pixar
Application granted granted Critical
Publication of CA1267230A publication Critical patent/CA1267230A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
CA000512328A 1985-06-24 1986-06-24 Selective operation of processing elements in a single instruction, multiple stream (simd) computer system Expired CA1267230A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74840985A 1985-06-24 1985-06-24
US748,409 1985-06-24

Publications (1)

Publication Number Publication Date
CA1267230A true CA1267230A (en) 1990-03-27

Family

ID=25009327

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000512328A Expired CA1267230A (en) 1985-06-24 1986-06-24 Selective operation of processing elements in a single instruction, multiple stream (simd) computer system

Country Status (8)

Country Link
EP (1) EP0227811A1 (ja)
JP (1) JPS6254359A (ja)
AU (1) AU6128486A (ja)
CA (1) CA1267230A (ja)
DE (1) DE3620982A1 (ja)
FR (1) FR2583904A1 (ja)
GB (1) GB2177526B (ja)
WO (1) WO1987000318A1 (ja)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2211638A (en) * 1987-10-27 1989-07-05 Ibm Simd array processor
GB2201015B (en) * 1987-02-10 1990-10-10 Univ Southampton Parallel processor array and array element
US5262965A (en) * 1988-10-31 1993-11-16 Bts-Broadcast Television Systems, Inc. System and method for high speed computer graphics image computation using a parallel connected, asynchronous multiprocessor ring coupled to a synchronous special purpose video processing ring
JP2578286Y2 (ja) * 1992-03-18 1998-08-06 日本精工株式会社 等速ジョイント
FR2693576B1 (fr) * 1992-07-13 1994-09-30 Texas Instruments France Système multiprocesseur à contrôle local.
FR2735253B1 (fr) * 1995-06-08 1999-10-22 Hewlett Packard Co Synchronisation de donnees entre plusieurs dispositifs de restitution asynchrones de donnees
AU717336B2 (en) * 1997-04-30 2000-03-23 Canon Kabushiki Kaisha Graphics processor architecture
US6366999B1 (en) * 1998-01-28 2002-04-02 Bops, Inc. Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
JPH11246581A (ja) * 1998-02-28 1999-09-14 Tonen Corp 亜鉛−モリブデン系ジチオカルバミン酸塩誘導体、その製造方法およびそれを含有する潤滑油組成物
US6732253B1 (en) 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US7434028B2 (en) * 2004-12-15 2008-10-07 Intel Corporation Hardware stack having entries with a data portion and associated counter
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
JP5452066B2 (ja) * 2009-04-24 2014-03-26 本田技研工業株式会社 並列計算装置
JP5358287B2 (ja) * 2009-05-19 2013-12-04 本田技研工業株式会社 並列計算装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
JPS56127266A (en) * 1980-03-10 1981-10-05 Ibm Method of executing and controlling command stream
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture

Also Published As

Publication number Publication date
AU6128486A (en) 1987-01-30
WO1987000318A1 (en) 1987-01-15
DE3620982A1 (de) 1987-01-29
JPH031699B2 (ja) 1991-01-11
GB2177526B (en) 1990-02-14
FR2583904A1 (fr) 1986-12-26
EP0227811A1 (en) 1987-07-08
GB2177526A (en) 1987-01-21
JPS6254359A (ja) 1987-03-10
GB8614907D0 (en) 1986-07-23

Similar Documents

Publication Publication Date Title
US5045995A (en) Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system
CA1267230A (en) Selective operation of processing elements in a single instruction, multiple stream (simd) computer system
US4398244A (en) Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same
US3689895A (en) Micro-program control system
US4835738A (en) Register stack for a bit slice processor microsequencer
US5276824A (en) Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe
US5008807A (en) Data processing apparatus with abbreviated jump field
US4467415A (en) High-speed microprogram control apparatus with decreased control storage requirements
US6026486A (en) General purpose processor having a variable bitwidth
GB1529581A (en) Data processing apparatus
US5019969A (en) Computer system for directly transferring vactor elements from register to register using a single instruction
US6904510B1 (en) Data processor having a respective multiplexer for each particular field
US7376811B2 (en) Method and apparatus for performing computations and operations on data using data steering
EP0239276A2 (en) Alu for a bit slice processor with multiplexed bypass path
KR100278136B1 (ko) 데이타처리장치 및 데이타처리방법
JPS61114341A (ja) 処理システム
JPH03288228A (ja) 情報処理装置
JP2555124B2 (ja) 画像処理装置
JPH0628198A (ja) Ｒｉｓｃマイクロプロセッサ優先ベクトル割り込みシステム
JPS6024642A (ja) マイクロプログラム制御方式
JPS6024643A (ja) マイクロプログラム制御方式
JPH0713759A (ja) 情報処理装置
JPH0425938A (ja) マイクロプログラム制御装置
JPH0375904B2 (ja)
JPH03252725A (ja) マイクロプログラム制御装置

Legal Events

Date Code Title Description
MKLA Lapsed