Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Definitions

• This invention relates generally to parallel data processing techniques and computer systems, and specifically to those of a type where each of a plurality of parallel processors simultaneously executes the same instruction on different data.
• a computer is commonly termed a single instruction, multiple data stream (SIMD) processor.
• SIMD single instruction, multiple data stream
• program being executed on the parallel streams of data is an invariant series of statements. It is more common, however, that the controlling program includes condi ⁇ tional statements that depend for execution upon the data in each of the parallel processors. Since the data being processed in each stream will be different, provision must be made in this case for those processors whose data does not meet the condition of the program statement to be rendered non-operative during the time that the remaining processors are executing the particular statement. It is known that a WHILE-DO construct is the minimum needed to implement all possible flow control structures.
• a common example of such a conditional program instruction is an "IF-THEN" statement: that is, the individual processors are all instructed to perform a certain manipulation of their individual data streams, but only "if" their data meets a certain condition expressed in the program instruction. Those processors whose data at that instant do not meet the condition do not execute that instruction.
• An "IF-THEN" instruction is often augmented by an "ELSE” modifier; that is, those processors not executing the "IF-THEN" statement are subsequently instructed to execute a different operation on their data at the next instant while those processors who did execute the "IF-THEN" instruction are rendered inoperative.
• each of the parallel processors has a separate control element, such as one bit of a control register, that enables the processor to execute a common, instruction given all processors when the element is in one state and disables the processor from executing that instruction when in its other state.
• the state of each control element is set to control execution , of a particular statement dependent upon whether the data for that processor met the test of a previous instruction, such as an "IF-THEN" instruction.
• subsequent complementary execution such as occurs in an "ELSE” instruction, the states of the control elements are reversed so that those processors who did not execute the first statement will execute the subsequent state ⁇ ment, and vice versa.
• a memory device (a stack memory in a preferred embodiment) is provided to store the states of the individual control elements when the nested condi- tional statement occurs.
• a memory device a stack memory in a preferred embodiment
• Figure 1 illustrates in general block diagram form a SIMD processor
• Figure 2 illustrates a first circuit embodiment
• Figures 3 and 4 are tables which illustrate the operation of the system of Figure 1 when implemented with the control circuit of Figure 2;
• Figure 5 illustrates a second circuit embodi ⁇ ment of the control circuits of the system of Figure 1;
• Figures 6 and 7 are tables which illustrate the operation of the system of Figure 1 whem implemented with the control circuit of Figure 5; and Figure 8 provides logic details of another portion of the circuit of Figure 1.
• Parallel processing is particularly adapted for a gra- phics application since high speed processing is a requirement and the same sequence of program instructions is executed simultaneously on all four data paths.
• a control circuit is provided in association with each of them, such as a circuit 37 which controls operation of the processing element 11.
• a line 39 carries a signal to the processing element 11 which controls whether it is enabled to execute an instruction on the bus 35. For example, a voltage in line 39 representative of a logical "1" will cause the processing element to execute the instruction, while a voltage representative of a logical "0" will disable the processing element during execution of that particular instruction by other of the processing elements.
• One is an initial condition which is presented external of the circuits of Figure 1 in a set line 41.
• Another piece of information is a status instruction in a bus 43 which specifies, for those processor instructions on bus 35 that may require less than all of the processing elements to execute the instruction, additional instructions for determining the state of the enable signal in the line 39.
• a final piece of information is a true "1" or false "0" signal in a line 45 which gives the result of a test performed by the processing element 11 on its data in response to a current or immediately preceding instruc-
• test result input received from its associated processing element can be different and thus result in some processors being enabled and others being disabled at a given instant in time.
• the function of the control circuits in the system of Figure 1 is explained more fully with respect to its two preferred embodiments, one embodiment illustrated in Figures 2-4 and another in Figures 5-7. But before proceeding to those embodiments, some general items of the system of Figure 1 are first explained.
• the pro ⁇ cessor instructions in the bus 35 and the status instructions 43 originate from a micro-programmed control unit such as micro-sequencer 47.
• a micro-programmed control unit consists of the micro-program memory and the structure required to determine the address of the next microinstruction, specific implementations being well known.
• a logic circuit 49 has as inputs the invidiual test result lines of each of the processing elements.
• the logic circuit 49 generates a condition code in an output line 51 when the signals in the input test result lines are a particular one or more combinations.
• the signal in the line 51 is connected to the condition code input of the micro-sequencer 47, thus enabling a change in the sequence of instructions in response to a particular combination of test result outputs.
• Another input to the logic circuits 49 is by way of a line 53, an instruction field of the micro-sequencer 47.
• each of the processing elements contains as primary components a 16-bit multiplier and a 16-bit arithmetic and logic unit (ALU).
• ALU arithmetic and logic unit
• a flip-flop circuit 61 has its output connected to the enable line 39.
• An input line 63 is connected to an output of a four-position multiplexer 65.
• the multiplexer 65 has four separate inputs 0-3.
• the status instruction in the bus 43 selects which of the inputs 0-3 is connected to the output 63.
• the 0 input of the multiplexer is connected directly to the output of the flip-flop 61, thereby allowing the current state of the flip-flop 61 to be held when the multiplexer 65 is switched to its 0 input.
• the next status instruction selecting the 1 input of the multi ⁇ plexer 65, causes the test result of its associated processing element to be stored, as previously described, an operation that accompanies an IF instruction in the bus 35.
• the status instruction 2 causes the flip-flop 61 to be set, a status instruction on bus 43 that accompanies an END IF instruction in the processing element instruction bus 35.
• a status instruction 3 causes the flip- flop element 61 to change state in order to enable those processors previously disabled, and conversely to disable those processors previously enabled.
• the status in ⁇ struction 3 is presented in the bus 43 simultaneously with the ELSE instruction in the bus 35.
• Micro-code in the micro-sequencer 47 assures that the instructions in the buses 35 and 43 correspond according to the table of Figure 3 in accordance with other particular requirements of any application.
• the table of Figure 4 better explains the operation of the circuit of Figure 1, when using a control circuit of Figure 2, by a specific example.
• IF statement asking whether the data input to each processing element .(D ) is greater than 1.
• line 2 of the table of Figure 4 it is assumed in the "test result" column that the first and third processing elements have passed the test, thus showing the logical "1" in their test result output lines 45, while the second and fourth processors have failed the test, and thus show a test result logical signal of "0".
• each processor is executing the same . IF instruction, the results of the test performed by each can be different because the data being processed by each is generally different.
• the status instruction on the bus 43 causes the multiplexer 65 of each of the control circuits of the system of Figure 1 to switch to its position 1 to receive the test results from their corresponding processors. These test results, whether a test pass "1" or fail "0", are then stored in the individual flip-flop elements.
• the enable signal outputs of the four flip-flops are given as the enable signals in the table of Figure 4, referred to interchangably in this example as "run flags".
• the runflags are causing those processing elements who pass the test to be enabled and those who did not to be disabled. Those which are enabled are then caused, as shown in the line 3 of the table of Figure 4, to execute a statement, in this example chosen to be to set the data output (D ) equal to 1 of the enabled processing elements.
• the disabled processing elements do nothing at this time.
• An ELSE instruction is next presented to all the processing elements for execution, which is to say that those processors who failed the IF test are now going to be called upon to do something different, as illus ⁇ trated in lines 4 and 5 of the. table of Figure 4.
• the ELSE processor instruction is accompanied by the status instruction 3 which causes the control circuits, illus- trated in Figure 2, to all invert the states of their flip-flops. That can be seen by comparing the run flags of lines 3 and 4 of Figure 4, one being the complement of the other.
• the logic circuits 49 of Figure 1 are useful for detecting conditions where, because of a particular combination of input data, certain instructions need not be executed. In such a case, the micro-sequencer 47 is then caused to skip the unexecutable instructions. Logic circuits 49 may be omitted in implementations where unexecuted instruction sequences may be allowed to occur. In the example of Figure 4, if the test results shown in line 2 had all been 0, then there is no need to execute the statement of line 3 since all processors would be disabled. For this particular example, therefore, the logic circuits 49 are designed to detect when all processor test results are false (0) and causes the condition code in the line 51 to change, with the resultant change of the instruction sequence issued by the micro-sequencer 47.
• test re ⁇ sults are all true (1)
• the instructions at lines 4 and 5 of Figure 4 do not need to be executed, so the condition code in the line 51 can cause that instruction sequence to be bypassed, as well.
• a signal in line 53 functions to allow testing for any false (0) condition or any true (1) condition.
• the ability is provided (in conjunction with the status instruction on the bus 43) for testing for any or all conditions true or false.
• An OR gate 52 has as its inputs the test result lines from all of the processing elements.
• the gate's output is one input of an exclusive OR gate 54, the select line 53 being the second input.
• the output of the gate 54 is the condition code line 51.
• the gate 54 operates to pass through the output of the gate 52 when the select line 53 is false (0), and to pass a complement of that output when the line 53 is true (1).
• Certain applications will require the ability of the individual processing element control circuits to handle a set of instructions that is nested within an IF- THEN-ELSE series of instructions.
• the run flags determined as the result of executing the IF instruction are stored while the nested set of instruc ⁇ tions is being executed. Once the nested instructions have been executed, the stored run flags are called out of memory so that the remainder of the IF-THEN-ELSE set of instructions can be executed.
• the control circuit of Figure 5 allows such • nested program instruction operation.
• a stacked memory 81 Added to the system circuit of Figure 1 is a stacked memory 81, and associated controlling decoder circuits 83.
• the cir ⁇ cuits within the dotted outline of Figure 5 are not repeated within each of the four control circuits of Figure 1, but rather are shared by them.
• the decoding circuits 83 respond to status instructions in the bus 43 to cause the current enable signals (run flags) of each of the control circuits to be stored in the stack memory 81 (a "push") through lines 85 or to be read from memory (a "pop") through lines 87.
• stack memories read ("pop") the last written ("pushed") data.
• a flip-flop 91 of the same type used in the embodiment of Figure 2 is employed, with this output being the enable signal, one bit of the four-bit run flag. Its input in a line 93 is also connected to an output of a multiplexer 95.
• the multiplexer has five positions 0-4, one more than used in the embodiment of Figure 2. One of these inputs is selected at a time for connection to the input of the flip-flop 91 by the status instruction in the bus 43. The 0 input is connected directly to the flip-flop output, thus serving to hold the flip-flop in whatever state it is found when switched to that position.
• Input 1 of the multiplexer receives the output of AND gate 97, having as one input the output of the flip-flop 91 and as the other input test result line 45 of its associated processor.
• the status instruction 1 is also decoded by circuits 83 to store ("push") at the top of the stack memory 81 the output (run flags) of the flip-flops within the control circuits of Figure 1.
• Multiplexer input 2 is connected to the set line 41.
• Input number 3 is connected to the stack memory 81 for setting the flip-flops in accordance with what has previously been recorded at the top of the stack.
• the decoding circuits 83 cause the top stack data of the memory 81 to pop when the status instruction 3 is received.
• the last input of the multiplexer 95 receives the output of another AND gate 99 whose two inputs are connected to the stack memory output and the output of the flip-flop 91 through an inverter 101.
• the result is to AND together the data stored at the top of the stack and a complement of the current run flags.
• the control circuit of Figure 5 whose logical operation is shown in the table of Figure 6, is especially adapted for carrying out the sequence of operations given in Figure 7.
• an IF-THEN-ELSE sequence of program instructions is executed at lines 1, 2, 3, 9, 10, 11, 17, 18, and 19. Nested inside the IF or ELSE portions of that set of instructions is yet another IF- THEN-ELSE series of instructions, at lines 4-8. Similarly, a second set of such statements is nested at lines 12-16 within the basic sequence of instructions.
• a different test result is assumed, as shown in the "test result" column of Figure 7. These different test results cause different run flags for each of the three IF-THEN- ELSE series of instructions.

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• 1986
  • 1986-06-19 GB GB8614907A patent/GB2177526B/en not_active Expired - Fee Related
  • 1986-06-23 AU AU61284/86A patent/AU6128486A/en not_active Abandoned
  • 1986-06-23 DE DE19863620982 patent/DE3620982A1/de not_active Withdrawn
  • 1986-06-23 WO PCT/US1986/001354 patent/WO1987000318A1/en unknown
  • 1986-06-23 EP EP19860904568 patent/EP0227811A1/en active Pending
  • 1986-06-24 JP JP14629086A patent/JPS6254359A/ja active Granted
  • 1986-06-24 FR FR8609106A patent/FR2583904A1/fr not_active Withdrawn
  • 1986-06-24 CA CA000512328A patent/CA1267230A/en not_active Expired

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