CA1134510A - Method and device for reduction of fibonacci p-codes to minimal form - Google Patents

Method and device for reduction of fibonacci p-codes to minimal form

Info

Publication number
CA1134510A
CA1134510A CA000282682A CA282682A CA1134510A CA 1134510 A CA1134510 A CA 1134510A CA 000282682 A CA000282682 A CA 000282682A CA 282682 A CA282682 A CA 282682A CA 1134510 A CA1134510 A CA 1134510A
Authority
CA
Canada
Prior art keywords
output
input
inputs
fibonacci
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000282682A
Other languages
English (en)
French (fr)
Inventor
Alexei P. Stakhov
Jury M. Vishnyakov
Vladimir A. Luzhetsky
Alexandr V. Ovodenko
Nikolai A. Solyanichenko
Alexandr V. Fomichev
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Original Assignee
Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova filed Critical Taganrogsky Radiotekhnichesky Institut Imeni VD Kalmykova
Application granted granted Critical
Publication of CA1134510A publication Critical patent/CA1134510A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Logic Circuits (AREA)
  • Detection And Correction Of Errors (AREA)
CA000282682A 1976-07-19 1977-07-14 Method and device for reduction of fibonacci p-codes to minimal form Expired CA1134510A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SU2386002 1976-07-19
SU762386002A SU662926A1 (ru) 1976-07-19 1976-07-19 Генератор последовательности обобщенных чисел фибоначчи с произвольными начальными услови ми

Publications (1)

Publication Number Publication Date
CA1134510A true CA1134510A (en) 1982-10-26

Family

ID=20670506

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000282682A Expired CA1134510A (en) 1976-07-19 1977-07-14 Method and device for reduction of fibonacci p-codes to minimal form

Country Status (9)

Country Link
US (1) US4187500A (enExample)
JP (1) JPS5333549A (enExample)
CA (1) CA1134510A (enExample)
DD (1) DD150514A1 (enExample)
DE (1) DE2732008C3 (enExample)
FR (1) FR2359460A1 (enExample)
GB (1) GB1543302A (enExample)
PL (1) PL108086B1 (enExample)
SU (7) SU662932A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2842672C2 (de) * 1978-09-29 1984-12-13 Vinnickij politechničeskij institut, Vinnica Digital-Analog-Umsetzer
DE2848911C2 (de) * 1978-11-10 1987-04-02 Vinnickij politechničeskij institut, Vinnica Digital/Analog-Wandler für gewichtete digitale Kodes
DE2921053C2 (de) * 1979-05-23 1985-10-17 Vinnickij politechničeskij institut, Vinnica Einrichtung zur Reduktion von n-stelligen Codes mit Irrationsbasis auf die Minimalform
GB2050011B (en) * 1979-05-25 1984-02-08 Vinnitsky Politekhn Inst Devices for reducing irrational base codes to minimal form
US4290051A (en) * 1979-07-30 1981-09-15 Stakhov Alexei P Device for reducing irrational-base codes to minimal form
WO1981003590A1 (en) * 1980-05-30 1981-12-10 Vinnitsky Politekhn Inst Converter of p-codes into analog values
GB2091507B (en) * 1980-06-26 1983-11-30 Vinnitsky Politekhn I Analog-to-digital converter
US4818969A (en) * 1984-08-09 1989-04-04 Kronos, Inc. Method of fixed-length binary encoding and decoding and apparatus for same
CN1110903C (zh) * 1995-02-03 2003-06-04 皇家菲利浦电子有限公司 编码装置和译码装置
ITRM20000347A1 (it) * 2000-06-26 2001-12-26 Salpiani Giampietro Metodo di rappresentazione numerica.
US6788224B2 (en) * 2000-06-26 2004-09-07 Atop Innovations S.P.A. Method for numeric compression and decompression of binary data
US6691283B1 (en) * 2001-12-12 2004-02-10 Lsi Logic Corporation Optimization of comparator architecture
CN101499001B (zh) * 2009-03-13 2010-09-29 天津工程师范学院 一种除数是127×2n的快速除法器

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032979A (en) * 1972-12-26 1977-06-28 Digital Development Corporation Method and system for encoding and decoding digital data

Also Published As

Publication number Publication date
DD150514A1 (de) 1981-09-02
SU662930A1 (ru) 1979-05-15
GB1543302A (en) 1979-04-04
FR2359460B1 (enExample) 1983-05-20
DE2732008B2 (de) 1981-07-09
DE2732008C3 (de) 1982-03-04
SU662926A1 (ru) 1979-05-15
PL108086B1 (pl) 1980-03-31
JPS5333549A (en) 1978-03-29
SU662931A1 (ru) 1979-05-15
SU662941A1 (ru) 1979-05-15
DE2732008A1 (de) 1978-02-02
PL199745A1 (pl) 1978-04-24
JPS5711459B2 (enExample) 1982-03-04
FR2359460A1 (fr) 1978-02-17
US4187500A (en) 1980-02-05
SU662934A1 (ru) 1979-05-15
SU662933A1 (ru) 1979-05-15
SU662932A1 (ru) 1979-05-15

Similar Documents

Publication Publication Date Title
CA1134510A (en) Method and device for reduction of fibonacci p-codes to minimal form
US3636334A (en) Parallel adder with distributed control to add a plurality of binary numbers
US3983382A (en) Adder with fast detection of sum equal to zeroes or radix minus one
CN106775577B (zh) 一种高性能非精确冗余二进制乘法器的设计方法
US3230353A (en) Pulse rate multiplier
US5113363A (en) Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing
GB963429A (en) Electronic binary parallel adder
US3311739A (en) Accumulative multiplier
US4873660A (en) Arithmetic processor using redundant signed digit arithmetic
CA1291267C (en) Counter
Chinal Design methods for digital systems
US3454751A (en) Binary adder circuit using denial logic
US3564225A (en) Serial binary coded decimal converter
US3159739A (en) Fast multiply apparatus
US3474236A (en) Bidirectional binary rate multiplier
US3271566A (en) Adding system for binary coded excess three numbers
US3535500A (en) Binary radix converter
US3925649A (en) Electronic computer for the static recognition of the divisibility, and the division of, numbers divisible by three, six and nine
GB790323A (en) Electrical checking circuit
US3389245A (en) Negabinary adders and subtractors
US3705299A (en) Circuit arrangement for converting a decimal number coded in the bcd code into a pure binary number
GB1565460A (en) Fibonacci code adders
US4094138A (en) Electronic chronograph
US3324288A (en) Data processing apparatus including means for correcting codes arranged in a packed format
US3505675A (en) Converter for binary and binary-coded decimal numbers

Legal Events

Date Code Title Description
MKEX Expiry