BRPI0909222A2 - Métodos paera formar uma arquitetura de camada amortecedora em silício e estruturas formadas por meio destes - Google Patents

Métodos paera formar uma arquitetura de camada amortecedora em silício e estruturas formadas por meio destes

Info

Publication number
BRPI0909222A2
BRPI0909222A2 BRPI0909222-6A BRPI0909222A BRPI0909222A2 BR PI0909222 A2 BRPI0909222 A2 BR PI0909222A2 BR PI0909222 A BRPI0909222 A BR PI0909222A BR PI0909222 A2 BRPI0909222 A2 BR PI0909222A2
Authority
BR
Brazil
Prior art keywords
methods
structures formed
cushioning layer
layer architecture
silicon
Prior art date
Application number
BRPI0909222-6A
Other languages
English (en)
Inventor
Mantu K Hudait
Peter G Tolchinsky
Loren A Chow
Dmitri Loubychev
Joel M Fastenau
Amy W K Liu
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BRPI0909222A2 publication Critical patent/BRPI0909222A2/pt

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02463Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02466Antimonides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122Single quantum well structures
    • H01L29/127Quantum box structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
BRPI0909222-6A 2008-06-19 2009-06-08 Métodos paera formar uma arquitetura de camada amortecedora em silício e estruturas formadas por meio destes BRPI0909222A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/214,737 US7687799B2 (en) 2008-06-19 2008-06-19 Methods of forming buffer layer architecture on silicon and structures formed thereby
PCT/US2009/046600 WO2009155157A2 (en) 2008-06-19 2009-06-08 Methods of forming buffer layer architecture on silicon and structures formed thereby

Publications (1)

Publication Number Publication Date
BRPI0909222A2 true BRPI0909222A2 (pt) 2015-08-25

Family

ID=41430277

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0909222-6A BRPI0909222A2 (pt) 2008-06-19 2009-06-08 Métodos paera formar uma arquitetura de camada amortecedora em silício e estruturas formadas por meio destes

Country Status (10)

Country Link
US (1) US7687799B2 (pt)
JP (1) JP5318940B2 (pt)
KR (1) KR101194465B1 (pt)
CN (1) CN101981657B (pt)
BR (1) BRPI0909222A2 (pt)
DE (1) DE112009000917B4 (pt)
GB (1) GB2473148B (pt)
RU (1) RU2468466C2 (pt)
TW (1) TWI383453B (pt)
WO (1) WO2009155157A2 (pt)

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GB2480265B (en) * 2010-05-10 2013-10-02 Toshiba Res Europ Ltd A semiconductor device and a method of fabricating a semiconductor device
CN102011182B (zh) * 2010-09-28 2013-03-13 中国电子科技集团公司第十八研究所 一种晶格渐变缓冲层的制备方法
KR101560239B1 (ko) 2010-11-18 2015-10-26 엘지디스플레이 주식회사 유기 발광 다이오드 표시장치와 그 구동방법
CN102157903B (zh) * 2011-01-25 2012-08-08 中国科学院半导体研究所 “w”型锑化物二类量子阱的外延生长方法
RU2520538C1 (ru) * 2012-11-02 2014-06-27 Федеральное государственное бюджетное учреждение науки Институт сверхвысокочастотной полупроводниковой электроники Российской академии наук (ИСВЧПЭ РАН) НАНОРАЗМЕРНАЯ СТРУКТУРА С КВАЗИОДНОМЕРНЫМИ ПРОВОДЯЩИМИ НИТЯМИ ОЛОВА В РЕШЕТКЕ GaAs
US20140151756A1 (en) * 2012-12-03 2014-06-05 International Business Machines Corporation Fin field effect transistors including complimentarily stressed channels
CN102983069A (zh) * 2012-12-21 2013-03-20 中国科学院半导体研究所 生长InP基InAs量子阱的方法
FR3011981B1 (fr) * 2013-10-11 2018-03-02 Centre National De La Recherche Scientifique - Cnrs - Transistor hemt a base d'heterojonction
JP6233070B2 (ja) * 2014-02-05 2017-11-22 住友電気工業株式会社 半導体積層体および半導体装置、ならびにそれらの製造方法
KR20160137977A (ko) * 2014-03-28 2016-12-02 인텔 코포레이션 선택적 에피택셜 성장된 iii-v족 재료 기반 디바이스
CN104600108B (zh) * 2014-12-31 2017-11-07 中国电子科技集团公司第五十五研究所 一种氮化物高电子迁移率晶体管外延结构及其制备方法
CN104733545A (zh) * 2015-02-17 2015-06-24 天津大学 发射区In含量渐变集电区高In过渡层的RTD器件
US9508550B2 (en) 2015-04-28 2016-11-29 International Business Machines Corporation Preparation of low defect density of III-V on Si for device fabrication
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RU2650576C2 (ru) * 2016-10-07 2018-04-16 Федеральное государственное бюджетное учреждение науки Институт сверхвысокочастотной полупроводниковой электроники Российской академии наук (ИСВЧПЭ РАН) Наноразмерная структура с профилем легирования в виде нанонитей из атомов олова
CN108493284B (zh) * 2018-05-03 2020-03-10 扬州乾照光电有限公司 一种晶格失配的多结太阳能电池及其制作方法
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Also Published As

Publication number Publication date
GB201015857D0 (en) 2010-10-27
JP2011518443A (ja) 2011-06-23
DE112009000917A5 (de) 2011-11-10
DE112009000917T5 (de) 2012-01-12
DE112009000917B4 (de) 2012-11-29
US20090315018A1 (en) 2009-12-24
GB2473148B (en) 2012-10-10
WO2009155157A2 (en) 2009-12-23
TW201009939A (en) 2010-03-01
JP5318940B2 (ja) 2013-10-16
KR101194465B1 (ko) 2012-10-24
TWI383453B (zh) 2013-01-21
WO2009155157A3 (en) 2010-03-18
RU2010139514A (ru) 2012-03-27
RU2468466C2 (ru) 2012-11-27
US7687799B2 (en) 2010-03-30
CN101981657A (zh) 2011-02-23
GB2473148A (en) 2011-03-02
KR20100114939A (ko) 2010-10-26
CN101981657B (zh) 2013-06-19

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2344 DE 08-12-2015 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.