BR112016000868A2 - - Google Patents

Info

Publication number
BR112016000868A2
BR112016000868A2 BR112016000868A BR112016000868A BR112016000868A2 BR 112016000868 A2 BR112016000868 A2 BR 112016000868A2 BR 112016000868 A BR112016000868 A BR 112016000868A BR 112016000868 A BR112016000868 A BR 112016000868A BR 112016000868 A2 BR112016000868 A2 BR 112016000868A2
Authority
BR
Brazil
Application number
BR112016000868A
Other languages
Portuguese (pt)
Other versions
BR112016000868B1 (pt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BR112016000868A2 publication Critical patent/BR112016000868A2/pt
Publication of BR112016000868B1 publication Critical patent/BR112016000868B1/pt

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/297Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
BR112016000868-5A 2013-07-16 2014-07-14 Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico BR112016000868B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361846648P 2013-07-16 2013-07-16
US61/846,648 2013-07-16
US14/013,399 2013-08-29
US14/013,399 US9418985B2 (en) 2013-07-16 2013-08-29 Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
PCT/US2014/046503 WO2015009614A1 (en) 2013-07-16 2014-07-14 Complete system-on-chip (soc) using monolithic three dimensional (3d) integrated circuit (ic) (3dic) technology

Publications (2)

Publication Number Publication Date
BR112016000868A2 true BR112016000868A2 (enExample) 2017-07-25
BR112016000868B1 BR112016000868B1 (pt) 2022-08-16

Family

ID=52343114

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016000868-5A BR112016000868B1 (pt) 2013-07-16 2014-07-14 Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico

Country Status (9)

Country Link
US (2) US9418985B2 (enExample)
EP (1) EP3022766A1 (enExample)
JP (1) JP2016529702A (enExample)
KR (1) KR101832330B1 (enExample)
CN (1) CN105378918B (enExample)
BR (1) BR112016000868B1 (enExample)
CA (1) CA2917586C (enExample)
TW (1) TWI618222B (enExample)
WO (1) WO2015009614A1 (enExample)

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CN105391823B (zh) * 2015-11-25 2019-02-12 上海新储集成电路有限公司 一种降低移动设备尺寸和功耗的方法
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US9712168B1 (en) * 2016-09-14 2017-07-18 Qualcomm Incorporated Process variation power control in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US10176147B2 (en) * 2017-03-07 2019-01-08 Qualcomm Incorporated Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods
US10727965B2 (en) * 2017-11-21 2020-07-28 Western Digital Technologies, Inc. System and method for time stamp synchronization
US10719100B2 (en) 2017-11-21 2020-07-21 Western Digital Technologies, Inc. System and method for time stamp synchronization
CN110069795A (zh) * 2018-01-23 2019-07-30 长芯半导体有限公司 快速定制芯片方法
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US11270917B2 (en) * 2020-06-01 2022-03-08 Alibaba Group Holding Limited Scalable and flexible architectures for integrated circuit (IC) design and fabrication
CN112769402B (zh) * 2020-12-21 2024-05-17 中国航天科工集团八五一一研究所 基于TSV技术的X/Ku波段宽带变频组件
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
KR102443742B1 (ko) * 2021-02-08 2022-09-15 고려대학교 산학협력단 모놀리식 3d 집적 기술 기반 스크래치패드 메모리
US12308072B2 (en) * 2021-03-10 2025-05-20 Invention And Collaboration Laboratory Pte. Ltd. Integrated scaling and stretching platform for optimizing monolithic integration and/or heterogeneous integration in a single semiconductor die
US12230607B2 (en) * 2021-03-31 2025-02-18 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including power management die in a stack and methods of forming the same
KR102896801B1 (ko) * 2022-02-23 2025-12-05 한국과학기술원 3차원 집적형 고주파 혼성 회로 구조체 및 그의 제조 방법
KR20240033841A (ko) 2022-09-06 2024-03-13 삼성전자주식회사 반도체 장치
WO2025117577A1 (en) * 2023-12-01 2025-06-05 The Penn State Research Foundation Monolithic three-dimensional (3d) integration of two dimensional (2d) field effect transistors (fets)

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Also Published As

Publication number Publication date
US20150022262A1 (en) 2015-01-22
EP3022766A1 (en) 2016-05-25
BR112016000868B1 (pt) 2022-08-16
JP2016529702A (ja) 2016-09-23
CN105378918A (zh) 2016-03-02
TWI618222B (zh) 2018-03-11
KR101832330B1 (ko) 2018-02-26
WO2015009614A1 (en) 2015-01-22
CA2917586C (en) 2019-02-12
US9418985B2 (en) 2016-08-16
US20160351553A1 (en) 2016-12-01
CA2917586A1 (en) 2015-01-22
KR20160032182A (ko) 2016-03-23
TW201513299A (zh) 2015-04-01
CN105378918B (zh) 2018-05-04
US9583473B2 (en) 2017-02-28

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 14/07/2014, OBSERVADAS AS CONDICOES LEGAIS