BR112015030050A2 - controle de temporização para receptor de sinal não correspondido - Google Patents
controle de temporização para receptor de sinal não correspondidoInfo
- Publication number
- BR112015030050A2 BR112015030050A2 BR112015030050A BR112015030050A BR112015030050A2 BR 112015030050 A2 BR112015030050 A2 BR 112015030050A2 BR 112015030050 A BR112015030050 A BR 112015030050A BR 112015030050 A BR112015030050 A BR 112015030050A BR 112015030050 A2 BR112015030050 A2 BR 112015030050A2
- Authority
- BR
- Brazil
- Prior art keywords
- clock distribution
- replica
- delay
- distribution network
- timing control
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dram (AREA)
- Pulse Circuits (AREA)
- Memory System (AREA)
Abstract
resumo patente de invenção: "controle de temporização para receptor de sinal não correspondido". trata-se de um dispositivo com uma interface de i/o que inclui uma réplica de um trajeto de distribuição de relógio correspondido a um trajeto de distribuição de relógio de um circuito receptor sem correspondência. o dispositivo pode monitorar mudanças no atraso na réplica de um trajeto, e ajustar o atraso no trajeto de distribuição de relógio real em resposta às mudanças de atraso detectadas na réplica de um trajeto. o circuito receptor inclui um trajeto de dados e uma rede de distribuição de relógio em uma configuração sem correspondência. um circuito de oscilador de anel inclui uma réplica de rede de distribuição de relógio correspondida à rede de distribuição de relógio real. portanto, as mudanças de atraso detectadas para a réplica de rede de distribuição de relógio indicam uma mudança no atraso na rede de distribuição de relógio real, que pode ser compensada em conformidade.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361841857P | 2013-07-01 | 2013-07-01 | |
US61/841,857 | 2013-07-01 | ||
US14/038,537 | 2013-09-26 | ||
US14/038,537 US9658642B2 (en) | 2013-07-01 | 2013-09-26 | Timing control for unmatched signal receiver |
PCT/US2014/045091 WO2015002973A1 (en) | 2013-07-01 | 2014-07-01 | Timing control for unmatched signal receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112015030050A2 true BR112015030050A2 (pt) | 2017-07-25 |
BR112015030050B1 BR112015030050B1 (pt) | 2021-02-09 |
Family
ID=52115588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112015030050-2A BR112015030050B1 (pt) | 2013-07-01 | 2014-07-01 | dispositivo de memória e controlador de memória para controle de temporização para receptor de sinal não correspondido |
Country Status (8)
Country | Link |
---|---|
US (2) | US9658642B2 (pt) |
EP (2) | EP3291237A1 (pt) |
JP (2) | JP6179836B2 (pt) |
KR (1) | KR101876619B1 (pt) |
CN (2) | CN108052479B (pt) |
BR (1) | BR112015030050B1 (pt) |
RU (1) | RU2632406C2 (pt) |
WO (1) | WO2015002973A1 (pt) |
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US8582374B2 (en) * | 2009-12-15 | 2013-11-12 | Intel Corporation | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system |
US9658642B2 (en) | 2013-07-01 | 2017-05-23 | Intel Corporation | Timing control for unmatched signal receiver |
KR20160041318A (ko) * | 2014-10-07 | 2016-04-18 | 에스케이하이닉스 주식회사 | 스트로브 신호 인터벌 검출 회로 및 이를 이용한 메모리 시스템 |
US10199082B2 (en) | 2016-01-18 | 2019-02-05 | Avago Technologies International Sales Pte. Limited | Automatic delay-line calibration using a replica array |
US10218360B2 (en) * | 2016-08-02 | 2019-02-26 | Altera Corporation | Dynamic clock-data phase alignment in a source synchronous interface circuit |
US20180059785A1 (en) * | 2016-08-23 | 2018-03-01 | International Business Machines Corporation | Remote Control Via Proximity Data |
US20180058846A1 (en) * | 2016-08-23 | 2018-03-01 | International Business Machines Corporation | Remote Control Via Proximity Data |
US9984740B1 (en) | 2017-03-21 | 2018-05-29 | Micron Technology, Inc. | Timing control for input receiver |
KR102499037B1 (ko) | 2018-01-10 | 2023-02-13 | 삼성전자주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
KR20200046245A (ko) | 2018-10-24 | 2020-05-07 | 삼성전자주식회사 | 메모리 모듈 및 메모리 시스템의 동작 방법 |
KR20200053219A (ko) * | 2018-11-08 | 2020-05-18 | 에스케이하이닉스 주식회사 | 복수의 클럭 경로를 포함하는 반도체 장치 및 시스템 |
US11175836B2 (en) | 2019-03-01 | 2021-11-16 | Qualcomm Incorporated | Enhanced data clock operations in memory |
JP2021150843A (ja) | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体集積回路、受信装置、及び受信装置の制御方法 |
CN113468840B (zh) * | 2020-03-30 | 2024-05-28 | 创意电子股份有限公司 | 时序模型的建立方法 |
KR20220006927A (ko) | 2020-07-09 | 2022-01-18 | 삼성전자주식회사 | 메모리 컨트롤러, 및 이를 포함하는 스토리지 장치, 및 메모리 시스템 |
US11726721B2 (en) * | 2020-09-09 | 2023-08-15 | Samsung Electronics Co., Ltd. | Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system |
KR20230134388A (ko) | 2022-03-14 | 2023-09-21 | 에스케이하이닉스 주식회사 | 반도체장치 |
EP4325492A4 (en) | 2022-07-08 | 2024-03-13 | Changxin Memory Technologies, Inc. | CONTROL DEVICE, MEMORY, SIGNAL PROCESSING METHOD AND ELECTRONIC DEVICE |
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JP2002358782A (ja) * | 2001-05-31 | 2002-12-13 | Nec Corp | 半導体記憶装置 |
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KR101585213B1 (ko) | 2009-08-18 | 2016-01-13 | 삼성전자주식회사 | 라이트 레벨링 동작을 수행하기 위한 메모리 장치의 제어 방법, 메모리 장치의 라이트 레벨링 방법, 및 라이트 레벨링 동작을 수행하는 메모리 컨트롤러, 메모리 장치, 및 메모리 시스템 |
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-
2013
- 2013-09-26 US US14/038,537 patent/US9658642B2/en active Active
-
2014
- 2014-07-01 EP EP17194019.0A patent/EP3291237A1/en not_active Ceased
- 2014-07-01 KR KR1020157033904A patent/KR101876619B1/ko active IP Right Grant
- 2014-07-01 BR BR112015030050-2A patent/BR112015030050B1/pt active IP Right Grant
- 2014-07-01 RU RU2015151605A patent/RU2632406C2/ru active
- 2014-07-01 WO PCT/US2014/045091 patent/WO2015002973A1/en active Application Filing
- 2014-07-01 CN CN201810010942.6A patent/CN108052479B/zh active Active
- 2014-07-01 CN CN201480031493.3A patent/CN105264605B/zh active Active
- 2014-07-01 EP EP14820637.8A patent/EP3017449B1/en active Active
- 2014-07-01 JP JP2016521920A patent/JP6179836B2/ja active Active
-
2017
- 2017-04-18 US US15/490,860 patent/US10324490B2/en active Active
- 2017-07-06 JP JP2017132562A patent/JP6409249B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
CN105264605B (zh) | 2019-03-08 |
US10324490B2 (en) | 2019-06-18 |
JP2016526724A (ja) | 2016-09-05 |
JP6409249B2 (ja) | 2018-10-24 |
CN108052479B (zh) | 2021-03-26 |
KR20160003811A (ko) | 2016-01-11 |
KR101876619B1 (ko) | 2018-07-09 |
EP3291237A1 (en) | 2018-03-07 |
US9658642B2 (en) | 2017-05-23 |
RU2632406C2 (ru) | 2017-10-04 |
EP3017449B1 (en) | 2018-09-12 |
JP2017208118A (ja) | 2017-11-24 |
EP3017449A1 (en) | 2016-05-11 |
US20170287539A1 (en) | 2017-10-05 |
BR112015030050B1 (pt) | 2021-02-09 |
CN108052479A (zh) | 2018-05-18 |
WO2015002973A1 (en) | 2015-01-08 |
JP6179836B2 (ja) | 2017-08-16 |
CN105264605A (zh) | 2016-01-20 |
EP3017449A4 (en) | 2017-02-08 |
US20150003574A1 (en) | 2015-01-01 |
RU2015151605A (ru) | 2017-06-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B06F | Objections, documents and/or translations needed after an examination request according art. 34 industrial property law | ||
B06U | Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure | ||
B09A | Decision: intention to grant | ||
B16A | Patent or certificate of addition of invention granted |
Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 01/07/2014, OBSERVADAS AS CONDICOES LEGAIS. |