BR112018001592A2 - chaveamento de relógio usando um circuito de retardo - Google Patents
chaveamento de relógio usando um circuito de retardoInfo
- Publication number
- BR112018001592A2 BR112018001592A2 BR112018001592A BR112018001592A BR112018001592A2 BR 112018001592 A2 BR112018001592 A2 BR 112018001592A2 BR 112018001592 A BR112018001592 A BR 112018001592A BR 112018001592 A BR112018001592 A BR 112018001592A BR 112018001592 A2 BR112018001592 A2 BR 112018001592A2
- Authority
- BR
- Brazil
- Prior art keywords
- clock signal
- signal
- delay circuit
- cgc
- latch
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0372—Bistable circuits of the master-slave type
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
trata-se de um aparelho que inclui um latch de um circuito de chaveamento de relógio (cgc). o latch é configurado para gerar um primeiro sinal em resposta a um sinal de relógio. o aparelho, inclui, ainda um circuito de retardo do cgc. o circuito de retardo é configurado para receber o sinal de relógio e gerar um segundo sinal com base no sinal de relógio e no primeiro sinal. o aparelho inclui, ainda, um circuito de saída do cgc. o circuito de saída é acoplado ao circuito de retardo e ao latch. o circuito de saída é configurado para gerar um sinal de relógio mestre com base no sinal de relógio e no segundo sinal. um bordo do sinal de relógio mestre é retardado em relação a um bordo do sinal de relógio com base em uma característica de retardo associada a um sinal de relógio escravo.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/810,243 US9837995B2 (en) | 2015-07-27 | 2015-07-27 | Clock gating using a delay circuit |
PCT/US2016/039568 WO2017019219A1 (en) | 2015-07-27 | 2016-06-27 | Clock gating using a delay circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112018001592A2 true BR112018001592A2 (pt) | 2018-09-18 |
Family
ID=56464289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112018001592A BR112018001592A2 (pt) | 2015-07-27 | 2016-06-27 | chaveamento de relógio usando um circuito de retardo |
Country Status (7)
Country | Link |
---|---|
US (1) | US9837995B2 (pt) |
EP (1) | EP3329341A1 (pt) |
JP (1) | JP2018529147A (pt) |
KR (1) | KR20180034431A (pt) |
CN (1) | CN107850919B (pt) |
BR (1) | BR112018001592A2 (pt) |
WO (1) | WO2017019219A1 (pt) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11671086B2 (en) | 2019-05-24 | 2023-06-06 | Sony Semiconductor Solutions Corporation | Circuit system |
TWI723667B (zh) * | 2019-12-05 | 2021-04-01 | 國立陽明交通大學 | 低電源雜訊的比較電路 |
TWI730707B (zh) * | 2020-04-01 | 2021-06-11 | 瑞昱半導體股份有限公司 | 時脈閘控單元 |
CN113497606B (zh) * | 2020-04-08 | 2024-02-23 | 瑞昱半导体股份有限公司 | 时脉闸控单元 |
US11894845B1 (en) * | 2022-08-30 | 2024-02-06 | Globalfoundries U.S. Inc. | Structure and method for delaying of data signal from pulse latch with lockup latch |
WO2024073194A1 (en) * | 2022-09-27 | 2024-04-04 | Qualcomm Incorporated | Design for testability for fault detection in clock gate control circuits |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100247477B1 (ko) | 1997-06-30 | 2000-03-15 | 김영환 | 비중복 2위상 클럭 간의 스큐 조절을 위한 클럭 장치 |
CN1224217A (zh) * | 1998-01-23 | 1999-07-28 | 三菱电机株式会社 | 防止无效数据输出的时钟同步半导体存贮装置 |
US7170819B2 (en) * | 2005-05-04 | 2007-01-30 | Infineon Technologies Ag | Integrated semiconductor memory device for synchronizing a signal with a clock signal |
US7323909B2 (en) | 2005-07-29 | 2008-01-29 | Sequence Design, Inc. | Automatic extension of clock gating technique to fine-grained power gating |
US20090119631A1 (en) | 2007-11-06 | 2009-05-07 | Jordi Cortadella | Variability-Aware Asynchronous Scheme for High-Performance Delay Matching |
US8103941B2 (en) | 2008-03-31 | 2012-01-24 | Globalfoundries Inc. | Low overhead soft error tolerant flip flop |
US7772889B2 (en) * | 2008-04-09 | 2010-08-10 | Globalfoundries Inc. | Programmable sample clock for empirical setup time selection |
US7772906B2 (en) | 2008-04-09 | 2010-08-10 | Advanced Micro Devices, Inc. | Low power flip flop through partially gated slave clock |
JP2010045483A (ja) | 2008-08-11 | 2010-02-25 | Nec Electronics Corp | クロックゲーティング回路 |
US8013654B1 (en) | 2008-12-17 | 2011-09-06 | Mediatek Inc. | Clock generator, pulse generator utilizing the clock generator, and methods thereof |
EP2320565A1 (en) | 2009-11-05 | 2011-05-11 | Nxp B.V. | A delay component |
US8058902B1 (en) * | 2010-06-11 | 2011-11-15 | Texas Instruments Incorporated | Circuit for aligning input signals |
GB2486003B (en) * | 2010-12-01 | 2016-09-14 | Advanced Risc Mach Ltd | Intergrated circuit, clock gating circuit, and method |
US8949652B2 (en) | 2011-11-03 | 2015-02-03 | Nvidia Corporation | Glitchless programmable clock shaper |
CN102857198B (zh) * | 2012-08-30 | 2015-09-30 | 锐迪科科技有限公司 | 用于双边沿触发器的时钟门控电路 |
US20140225655A1 (en) | 2013-02-14 | 2014-08-14 | Qualcomm Incorporated | Clock-gated synchronizer |
US9213358B2 (en) | 2013-10-31 | 2015-12-15 | Qualcomm Incorporated | Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components |
-
2015
- 2015-07-27 US US14/810,243 patent/US9837995B2/en active Active
-
2016
- 2016-06-27 EP EP16741181.8A patent/EP3329341A1/en not_active Withdrawn
- 2016-06-27 BR BR112018001592A patent/BR112018001592A2/pt not_active Application Discontinuation
- 2016-06-27 JP JP2018503645A patent/JP2018529147A/ja active Pending
- 2016-06-27 KR KR1020187002357A patent/KR20180034431A/ko unknown
- 2016-06-27 CN CN201680039998.3A patent/CN107850919B/zh not_active Expired - Fee Related
- 2016-06-27 WO PCT/US2016/039568 patent/WO2017019219A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
KR20180034431A (ko) | 2018-04-04 |
EP3329341A1 (en) | 2018-06-06 |
US20170033775A1 (en) | 2017-02-02 |
US9837995B2 (en) | 2017-12-05 |
JP2018529147A (ja) | 2018-10-04 |
WO2017019219A1 (en) | 2017-02-02 |
CN107850919A (zh) | 2018-03-27 |
CN107850919B (zh) | 2021-08-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B11A | Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing | ||
B11Y | Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired |