BR112016023615A2 - capacitor de pacote comutável para conservação de carga e resistência em série - Google Patents

capacitor de pacote comutável para conservação de carga e resistência em série

Info

Publication number
BR112016023615A2
BR112016023615A2 BR112016023615A BR112016023615A BR112016023615A2 BR 112016023615 A2 BR112016023615 A2 BR 112016023615A2 BR 112016023615 A BR112016023615 A BR 112016023615A BR 112016023615 A BR112016023615 A BR 112016023615A BR 112016023615 A2 BR112016023615 A2 BR 112016023615A2
Authority
BR
Brazil
Prior art keywords
resistance
switchable
conservation
series
capacitor
Prior art date
Application number
BR112016023615A
Other languages
English (en)
Inventor
Popovich Mikhail
Michael Coutts Ryan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016023615A2 publication Critical patent/BR112016023615A2/pt

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/647Resistive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Computing Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Attenuators (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

trata-se, em uma modalidade, de um aparelho que compreende um capacitor e uma matriz. a matriz compreende um comutador de resistor acoplado entre uma linha de potência e o capacitor, em que o comutador de resistor tem uma resistência ajustável, e a linha de potência e o capacitor são ambos externos em relação à matriz. a matriz também compreende um circuito configurado para receber potência a partir da linha de potência.
BR112016023615A 2014-04-10 2015-03-09 capacitor de pacote comutável para conservação de carga e resistência em série BR112016023615A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/250,150 US9377804B2 (en) 2014-04-10 2014-04-10 Switchable package capacitor for charge conservation and series resistance
PCT/US2015/019526 WO2015156940A2 (en) 2014-04-10 2015-03-09 Switchable package capacitor for charge conservation and series resistance

Publications (1)

Publication Number Publication Date
BR112016023615A2 true BR112016023615A2 (pt) 2017-08-15

Family

ID=52697567

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016023615A BR112016023615A2 (pt) 2014-04-10 2015-03-09 capacitor de pacote comutável para conservação de carga e resistência em série

Country Status (7)

Country Link
US (2) US9377804B2 (pt)
EP (1) EP3130008B1 (pt)
JP (2) JP6509904B2 (pt)
KR (1) KR102154089B1 (pt)
CN (1) CN106170739B (pt)
BR (1) BR112016023615A2 (pt)
WO (1) WO2015156940A2 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9377804B2 (en) 2014-04-10 2016-06-28 Qualcomm Incorporated Switchable package capacitor for charge conservation and series resistance
US20160173082A1 (en) * 2014-12-12 2016-06-16 Mediatek Inc. Method for performing impedance profile control of a power delivery network in an electronic device, and associated apparatus
US10581414B2 (en) * 2015-10-14 2020-03-03 Mediatek Inc. Semiconductor integrated circuit device
US10664035B2 (en) * 2017-08-31 2020-05-26 Qualcomm Incorporated Reconfigurable power delivery networks
US11437366B2 (en) * 2017-09-29 2022-09-06 Intel Corporation Tunable passive semiconductor elements
JP6652998B1 (ja) * 2018-09-03 2020-02-26 レノボ・シンガポール・プライベート・リミテッド 情報処理装置および制御方法
CN117219145A (zh) * 2020-08-06 2023-12-12 长江存储科技有限责任公司 用于三维存储器的多管芯峰值功率管理
EP4147238A4 (en) 2020-11-26 2023-11-01 Yangtze Memory Technologies Co., Ltd. DYNAMIC PEAK POWER MANAGEMENT FOR MULTIPLE CHIP OPERATIONS

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US6700390B2 (en) 2002-05-31 2004-03-02 Sun Microsystems, Inc. Adjustment and calibration system to store resistance settings to control chip/package resonance
JP4107052B2 (ja) * 2002-10-30 2008-06-25 株式会社デンソー 多出力電源装置
US6949810B2 (en) 2003-10-14 2005-09-27 Intel Corporation Active phase cancellation for power delivery
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US9377804B2 (en) 2014-04-10 2016-06-28 Qualcomm Incorporated Switchable package capacitor for charge conservation and series resistance

Also Published As

Publication number Publication date
US20160266596A1 (en) 2016-09-15
WO2015156940A3 (en) 2015-12-23
EP3130008A2 (en) 2017-02-15
JP2019145814A (ja) 2019-08-29
EP3130008B1 (en) 2020-04-29
US20150293551A1 (en) 2015-10-15
US9377804B2 (en) 2016-06-28
CN106170739A (zh) 2016-11-30
US9618957B2 (en) 2017-04-11
CN106170739B (zh) 2017-10-13
JP6509904B2 (ja) 2019-05-08
WO2015156940A2 (en) 2015-10-15
KR20160140712A (ko) 2016-12-07
KR102154089B1 (ko) 2020-09-09
JP2017520104A (ja) 2017-07-20

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B11D Dismissal acc. art. 38, par 2 of ipl - failure to pay fee after grant in time