BR0307364A - Método para embutir um componente em uma base e produzir um contato - Google Patents
Método para embutir um componente em uma base e produzir um contatoInfo
- Publication number
- BR0307364A BR0307364A BR0307364-5A BR0307364A BR0307364A BR 0307364 A BR0307364 A BR 0307364A BR 0307364 A BR0307364 A BR 0307364A BR 0307364 A BR0307364 A BR 0307364A
- Authority
- BR
- Brazil
- Prior art keywords
- base
- conductive pattern
- semiconductor components
- component
- contact
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Combinations Of Printed Boards (AREA)
- Auxiliary Devices For And Details Of Packaging Control (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Reverberation, Karaoke And Other Acoustics (AREA)
- Structure Of Printed Boards (AREA)
Abstract
"MéTODO PARA EMBUTIR UM COMPONENTE EM UMA BASE E PRODUZIR UM CONTATO". A presente invenção divulga um método em que componentes semicondutores que fazem parte de um circuito eletrónico, ou pelo menos alguns dos mesmos, são embutidos em uma base, tal como um painel de circuito, durante a fabricação da base. Assim, a estrutura da base é mais ou menos fabricada em torno do componente semicondutor. De acordo com a invenção, em primeiro lugar, são feitos na base pelo menos três padrões condutores e furos vazados para os componentes semicondutores. Em seguida, os componentes semicondutores são colocados nos furos em alinhamento com o padrão condutor. Os componentes semicondutores são fixados à estrutura da base e uma ou mais camadas de padrões condutores são feitas na base, de tal modo que pelo menos um padrão condutor forme um contato elétrico com as áreas de contato da superfície do componente semicondutor.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20020190A FI115285B (fi) | 2002-01-31 | 2002-01-31 | Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi |
PCT/FI2003/000064 WO2003065778A1 (en) | 2002-01-31 | 2003-01-28 | Method for embedding a component in a base and forming a contact |
Publications (2)
Publication Number | Publication Date |
---|---|
BR0307364A true BR0307364A (pt) | 2004-12-14 |
BRPI0307364B1 BRPI0307364B1 (pt) | 2017-02-21 |
Family
ID=8563006
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI0307364A BRPI0307364B1 (pt) | 2002-01-31 | 2003-01-28 | método para embutir um componente em uma base e produzir um contato, e módulo eletrônico fabricado usando o referido método |
Country Status (13)
Country | Link |
---|---|
US (1) | US6991966B2 (pt) |
EP (1) | EP1474959B1 (pt) |
JP (1) | JP2005517287A (pt) |
KR (2) | KR101013325B1 (pt) |
CN (1) | CN100566511C (pt) |
AT (1) | ATE295064T1 (pt) |
BR (1) | BRPI0307364B1 (pt) |
DE (1) | DE60300619T2 (pt) |
FI (1) | FI115285B (pt) |
HK (1) | HK1077151A1 (pt) |
IL (1) | IL163238A (pt) |
RU (1) | RU2297736C2 (pt) |
WO (1) | WO2003065778A1 (pt) |
Families Citing this family (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1901181B (zh) * | 2000-09-25 | 2012-09-05 | 揖斐电株式会社 | 半导体元件及其制造方法、多层印刷布线板及其制造方法 |
US8704359B2 (en) * | 2003-04-01 | 2014-04-22 | Ge Embedded Electronics Oy | Method for manufacturing an electronic module and an electronic module |
FI115601B (fi) * | 2003-04-01 | 2005-05-31 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli |
US8222723B2 (en) | 2003-04-01 | 2012-07-17 | Imbera Electronics Oy | Electric module having a conductive pattern layer |
US7547975B2 (en) * | 2003-07-30 | 2009-06-16 | Tdk Corporation | Module with embedded semiconductor IC and method of fabricating the module |
FI20031201A (fi) * | 2003-08-26 | 2005-02-27 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli |
FI20031341A (fi) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
FI20040592A (fi) | 2004-04-27 | 2005-10-28 | Imbera Electronics Oy | Lämmön johtaminen upotetusta komponentista |
FI117814B (fi) | 2004-06-15 | 2007-02-28 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
US8487194B2 (en) * | 2004-08-05 | 2013-07-16 | Imbera Electronics Oy | Circuit board including an embedded component |
FI117812B (fi) * | 2004-08-05 | 2007-02-28 | Imbera Electronics Oy | Komponentin sisältävän kerroksen valmistaminen |
JP4148201B2 (ja) * | 2004-08-11 | 2008-09-10 | ソニー株式会社 | 電子回路装置 |
US7615856B2 (en) * | 2004-09-01 | 2009-11-10 | Sanyo Electric Co., Ltd. | Integrated antenna type circuit apparatus |
TWI241007B (en) * | 2004-09-09 | 2005-10-01 | Phoenix Prec Technology Corp | Semiconductor device embedded structure and method for fabricating the same |
TW200618705A (en) | 2004-09-16 | 2006-06-01 | Tdk Corp | Multilayer substrate and manufacturing method thereof |
FI117369B (fi) | 2004-11-26 | 2006-09-15 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
US7410907B2 (en) * | 2005-03-31 | 2008-08-12 | Lucent Technologies Inc. | Fabricating integrated devices using embedded masks |
KR100651562B1 (ko) * | 2005-06-14 | 2006-11-29 | 삼성전기주식회사 | 전자부품 내장형 회로기판의 제조방법 |
GB2441265B (en) | 2005-06-16 | 2012-01-11 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
FI122128B (fi) * | 2005-06-16 | 2011-08-31 | Imbera Electronics Oy | Menetelmä piirilevyrakenteen valmistamiseksi |
FI119714B (fi) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi |
JP2007012761A (ja) * | 2005-06-29 | 2007-01-18 | Tdk Corp | 半導体ic内蔵基板及びその製造方法 |
US8829661B2 (en) | 2006-03-10 | 2014-09-09 | Freescale Semiconductor, Inc. | Warp compensated package and method |
JP3942190B1 (ja) * | 2006-04-25 | 2007-07-11 | 国立大学法人九州工業大学 | 両面電極構造の半導体装置及びその製造方法 |
KR100796523B1 (ko) * | 2006-08-17 | 2008-01-21 | 삼성전기주식회사 | 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법 |
US8021981B2 (en) | 2006-08-30 | 2011-09-20 | Micron Technology, Inc. | Redistribution layers for microfeature workpieces, and associated systems and methods |
KR100769527B1 (ko) * | 2006-09-19 | 2007-10-23 | 삼성전기주식회사 | 임베디드 인쇄회로기판 및 그 제조방법 |
US20080123318A1 (en) * | 2006-11-08 | 2008-05-29 | Atmel Corporation | Multi-component electronic package with planarized embedded-components substrate |
KR100788213B1 (ko) * | 2006-11-21 | 2007-12-26 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판의 제조방법 |
US9953910B2 (en) | 2007-06-21 | 2018-04-24 | General Electric Company | Demountable interconnect structure |
US20080318413A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and interconnect component recovery process |
US9610758B2 (en) * | 2007-06-21 | 2017-04-04 | General Electric Company | Method of making demountable interconnect structure |
US20080313894A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and low-temperature interconnect component recovery process |
US20080318055A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Recoverable electronic component |
US20080318054A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Low-temperature recoverable electronic component |
WO2009001621A1 (ja) * | 2007-06-26 | 2008-12-31 | Murata Manufacturing Co., Ltd. | 部品内蔵基板の製造方法 |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
JPWO2009118925A1 (ja) | 2008-03-27 | 2011-07-21 | イビデン株式会社 | 電子部品内蔵配線板及びその製造方法 |
US8259454B2 (en) * | 2008-04-14 | 2012-09-04 | General Electric Company | Interconnect structure including hybrid frame panel |
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-
2002
- 2002-01-31 FI FI20020190A patent/FI115285B/fi not_active IP Right Cessation
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2003
- 2003-01-28 JP JP2003565216A patent/JP2005517287A/ja active Pending
- 2003-01-28 KR KR1020047011833A patent/KR101013325B1/ko active IP Right Grant
- 2003-01-28 WO PCT/FI2003/000064 patent/WO2003065778A1/en active Application Filing
- 2003-01-28 DE DE60300619T patent/DE60300619T2/de not_active Expired - Lifetime
- 2003-01-28 KR KR1020107023652A patent/KR20100126546A/ko not_active Application Discontinuation
- 2003-01-28 AT AT03700815T patent/ATE295064T1/de active
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- 2003-01-28 EP EP03700815A patent/EP1474959B1/en not_active Expired - Lifetime
- 2003-01-28 CN CNB038031353A patent/CN100566511C/zh not_active Expired - Lifetime
- 2003-01-28 RU RU2004126137/09A patent/RU2297736C2/ru active
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DE60300619D1 (de) | 2005-06-09 |
IL163238A (en) | 2009-06-15 |
FI20020190A0 (fi) | 2002-01-31 |
US6991966B2 (en) | 2006-01-31 |
CN1625927A (zh) | 2005-06-08 |
BRPI0307364B1 (pt) | 2017-02-21 |
US20050124148A1 (en) | 2005-06-09 |
DE60300619T2 (de) | 2006-01-19 |
KR20040073606A (ko) | 2004-08-19 |
ATE295064T1 (de) | 2005-05-15 |
HK1077151A1 (en) | 2006-02-03 |
FI20020190A (fi) | 2003-08-01 |
FI115285B (fi) | 2005-03-31 |
RU2004126137A (ru) | 2005-06-10 |
KR101013325B1 (ko) | 2011-02-09 |
EP1474959B1 (en) | 2005-05-04 |
JP2005517287A (ja) | 2005-06-09 |
CN100566511C (zh) | 2009-12-02 |
RU2297736C2 (ru) | 2007-04-20 |
WO2003065778A1 (en) | 2003-08-07 |
KR20100126546A (ko) | 2010-12-01 |
EP1474959A1 (en) | 2004-11-10 |
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