BR0306689A - Aparelho e método de intercalação para um sistema de comunicação - Google Patents

Aparelho e método de intercalação para um sistema de comunicação

Info

Publication number
BR0306689A
BR0306689A BR0306689-4A BR0306689A BR0306689A BR 0306689 A BR0306689 A BR 0306689A BR 0306689 A BR0306689 A BR 0306689A BR 0306689 A BR0306689 A BR 0306689A
Authority
BR
Brazil
Prior art keywords
memory
interleaving
interleaver
addresses
interleaver size
Prior art date
Application number
BR0306689-4A
Other languages
English (en)
Other versions
BRPI0306689B1 (pt
Inventor
Min-Goo Kim
Sang-Hyuck Ha
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of BR0306689A publication Critical patent/BR0306689A/pt
Publication of BRPI0306689B1 publication Critical patent/BRPI0306689B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2789—Interleaver providing variable interleaving, e.g. variable block sizes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

"APARELHO E MéTODO DE INTERCALAçãO PARA UM SISTEMA DE COMUNICAçãO". Aparelho e método de intercalação para determinar um novo tamanho de intercalador N<39=2^ m^x(j+1) e endereços de 0 a N<39>-1, se um dado tamanho de intercalador N for maior que 2<39>xj e menor que 2<39>x(j+1), onde m representa um primeiro parâmetro que indica um número de bits consecutivos zero desde um bit menos significativo (LSB) até um bit mais significativo (MSB), e j representa um segundo parâmetro que corresponde a um valor decimal exceto os referidos bits consecutivos zero. O aparelho e método de intercalação armazenam seq³encialmente N bits de dados de entrada em uma memória de intercalador com o novo tamanho de intercalador N, desde um endereço O até um endereço N-1. O aparelho e método de intercalação executam em seguida uma intercalação de Inversão Parcial de Bits (PBRO) da memória com o novo tamanho de intercalador N<39> e lêem dados da memória pela eliminação de endereços correspondentes a endereços de N a N<39>-1 da memória antes de intercalação.
BRPI0306689A 2002-01-09 2003-01-09 aparelho e método de intercalação para um sistema de comunicação BRPI0306689B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020020001252A KR100860660B1 (ko) 2002-01-09 2002-01-09 통신시스템의 인터리빙 장치 및 방법
PCT/KR2003/000033 WO2003058823A1 (en) 2002-01-09 2003-01-09 Interleaving apparatus and method for a communication system

Publications (2)

Publication Number Publication Date
BR0306689A true BR0306689A (pt) 2004-12-07
BRPI0306689B1 BRPI0306689B1 (pt) 2016-11-16

Family

ID=19718325

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0306689A BRPI0306689B1 (pt) 2002-01-09 2003-01-09 aparelho e método de intercalação para um sistema de comunicação

Country Status (10)

Country Link
US (1) US6910110B2 (pt)
EP (1) EP1330040B1 (pt)
JP (1) JP3958745B2 (pt)
KR (1) KR100860660B1 (pt)
CN (2) CN100539443C (pt)
AU (1) AU2003202155B2 (pt)
BR (1) BRPI0306689B1 (pt)
CA (1) CA2472952C (pt)
RU (1) RU2274950C2 (pt)
WO (1) WO2003058823A1 (pt)

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US7401208B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor
US7360062B2 (en) * 2003-04-25 2008-04-15 International Business Machines Corporation Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
US7398446B2 (en) * 2003-05-29 2008-07-08 Lucent Technologies Inc. Low power operation of an address interleaver
US7069398B2 (en) * 2003-06-20 2006-06-27 Industrial Technology Research Institute Apparatus and method for de-interleaving the interleaved data in a coded orthogonal frequency division multiplexing receiver
WO2005052798A1 (en) * 2003-11-26 2005-06-09 Cygnus Communications Canada Co. Interleaving memory
US7415584B2 (en) 2003-11-26 2008-08-19 Cygnus Communications Canada Co. Interleaving input sequences to memory
MX2007001166A (es) * 2004-07-29 2007-07-11 Qualcomm Inc Sistema y metodo para intercalacion.
US9246728B2 (en) 2004-07-29 2016-01-26 Qualcomm Incorporated System and method for frequency diversity
KR100853497B1 (ko) * 2004-08-25 2008-08-21 삼성전자주식회사 터보 인터리빙 장치 및 그의 출력주소 발생 방법
US7167114B2 (en) * 2004-10-05 2007-01-23 Sony Corporation Memory efficient interleaving
KR100762134B1 (ko) 2004-10-07 2007-10-02 엘지전자 주식회사 블록 인터리빙을 위한 읽기 주소 발생 방법
US7543197B2 (en) * 2004-12-22 2009-06-02 Qualcomm Incorporated Pruned bit-reversal interleaver
KR100699491B1 (ko) * 2005-07-19 2007-03-26 삼성전자주식회사 인터리빙 방법 및 그 장치
US9391751B2 (en) 2005-07-29 2016-07-12 Qualcomm Incorporated System and method for frequency diversity
US9042212B2 (en) 2005-07-29 2015-05-26 Qualcomm Incorporated Method and apparatus for communicating network identifiers in a communication system
US7555684B1 (en) * 2006-01-17 2009-06-30 Xilinx, Inc. Circuit for and a method of generating an interleaver address
US20070277064A1 (en) * 2006-05-02 2007-11-29 Mediatek Inc. Reconfigurable convolutional interleaver/deinterleaver using minimum amount of memory and an address generator
US8266508B2 (en) * 2007-06-08 2012-09-11 Telefonaktiebolaget L M Ericsson (Publ) Computational efficient convolutional coding with rate matching
KR101435830B1 (ko) * 2007-06-20 2014-08-29 엘지전자 주식회사 인터리빙 수행 방법
US9712279B2 (en) 2007-10-04 2017-07-18 Samsung Electronics Co., Ltd. Method and apparatus for interleaving data in a mobile communication system
KR101613893B1 (ko) * 2007-10-04 2016-04-20 삼성전자주식회사 이동통신 시스템에서 데이터 인터리빙 방법 및 장치
GB2456775B (en) * 2008-01-22 2012-10-31 Advanced Risc Mach Ltd Apparatus and method for performing permutation operations on data
US8127105B2 (en) * 2008-11-04 2012-02-28 Qualcomm Incorporated Parallel pruned bit-reversal interleaver
CN101710850B (zh) 2008-12-26 2013-10-30 三星电子株式会社 卷积Turbo编码方法及实现编码方法的设备
US8572148B1 (en) * 2009-02-23 2013-10-29 Xilinx, Inc. Data reorganizer for fourier transformation of parallel data streams
US8775750B2 (en) 2009-09-16 2014-07-08 Nec Corporation Interleaver with parallel address queue arbitration dependent on which queues are empty
EP2706667A1 (en) 2010-09-13 2014-03-12 Hughes Network Systems, LLC Method and apparatus for a parameterized interleaver design process
US9268691B2 (en) 2012-06-11 2016-02-23 Intel Corporation Fast mechanism for accessing 2n±1 interleaved memory system
MX2018005575A (es) * 2015-11-10 2018-08-01 Sony Corp Aparato de procesamiento de datos, y metodo de procesamiento de datos.
CN109474373B (zh) * 2017-09-08 2021-01-29 华为技术有限公司 交织方法和交织装置

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US6198733B1 (en) * 1998-03-13 2001-03-06 Lucent Technologies Inc. Forward-link sync-channel interleaving/de-interleaving for communication systems based on closed-form expressions
US6466564B1 (en) * 1998-09-14 2002-10-15 Terayon Communications Systems, Inc. Two dimensional interleave process for CDMA transmissions of one dimensional timeslot data
US6304991B1 (en) * 1998-12-04 2001-10-16 Qualcomm Incorporated Turbo code interleaver using linear congruential sequence
KR100306282B1 (ko) * 1998-12-10 2001-11-02 윤종용 통신시스템의인터리빙/디인터리빙장치및방법
KR100346170B1 (ko) * 1998-12-21 2002-11-30 삼성전자 주식회사 통신시스템의인터리빙/디인터리빙장치및방법
KR100350459B1 (ko) * 1998-12-26 2002-12-26 삼성전자 주식회사 통신시스템의인터리빙/디인터리빙장치및방법
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KR100724921B1 (ko) * 2001-02-16 2007-06-04 삼성전자주식회사 통신시스템에서 부호 생성 및 복호 장치 및 방법

Also Published As

Publication number Publication date
JP3958745B2 (ja) 2007-08-15
AU2003202155B2 (en) 2006-07-06
CN100539443C (zh) 2009-09-09
CA2472952A1 (en) 2003-07-17
KR20030060518A (ko) 2003-07-16
EP1330040B1 (en) 2012-10-03
US6910110B2 (en) 2005-06-21
EP1330040A3 (en) 2003-07-30
CN101615915A (zh) 2009-12-30
US20030149849A1 (en) 2003-08-07
RU2004121027A (ru) 2005-05-27
CN1615592A (zh) 2005-05-11
KR100860660B1 (ko) 2008-09-26
WO2003058823A1 (en) 2003-07-17
BRPI0306689B1 (pt) 2016-11-16
CA2472952C (en) 2008-04-01
EP1330040A2 (en) 2003-07-23
RU2274950C2 (ru) 2006-04-20
JP2005514848A (ja) 2005-05-19
AU2003202155A1 (en) 2003-07-24

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: A CLASSIFICACAO ANTERIOR ERA: H03M 13/27

Ipc: H04L 1/00 (2006.01), H03M 13/27 (2006.01)

B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 16/11/2016, OBSERVADAS AS CONDICOES LEGAIS.