ATE528790T1 - Verfahren zum schnellen tempern von mehrschicht- wafern mit einer kante - Google Patents

Verfahren zum schnellen tempern von mehrschicht- wafern mit einer kante

Info

Publication number
ATE528790T1
ATE528790T1 AT03772490T AT03772490T ATE528790T1 AT E528790 T1 ATE528790 T1 AT E528790T1 AT 03772490 T AT03772490 T AT 03772490T AT 03772490 T AT03772490 T AT 03772490T AT E528790 T1 ATE528790 T1 AT E528790T1
Authority
AT
Austria
Prior art keywords
rapid
temping
wafer
edge
heat treatment
Prior art date
Application number
AT03772490T
Other languages
English (en)
Inventor
Eric Neyret
Christophe Malleville
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE528790T1 publication Critical patent/ATE528790T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0432—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Formation Of Insulating Films (AREA)
AT03772490T 2002-11-05 2003-11-03 Verfahren zum schnellen tempern von mehrschicht- wafern mit einer kante ATE528790T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0213810A FR2846786B1 (fr) 2002-11-05 2002-11-05 Procede de recuit thermique rapide de tranches a couronne
FR0300286A FR2846787B1 (fr) 2002-11-05 2003-01-13 Procede de recuit thermique rapide de tranches a couronne
PCT/IB2003/005295 WO2004042802A2 (en) 2002-11-05 2003-11-03 A method of rapidly thermally annealing multilayer wafers with an edge

Publications (1)

Publication Number Publication Date
ATE528790T1 true ATE528790T1 (de) 2011-10-15

Family

ID=32109208

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03772490T ATE528790T1 (de) 2002-11-05 2003-11-03 Verfahren zum schnellen tempern von mehrschicht- wafern mit einer kante

Country Status (10)

Country Link
US (2) US6853802B2 (de)
EP (2) EP2330616A3 (de)
JP (1) JP4772501B2 (de)
KR (1) KR100814998B1 (de)
CN (1) CN100541739C (de)
AT (1) ATE528790T1 (de)
AU (1) AU2003280109A1 (de)
FR (2) FR2846786B1 (de)
TW (1) TWI278937B (de)
WO (1) WO2004042802A2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2846786B1 (fr) * 2002-11-05 2005-06-17 Procede de recuit thermique rapide de tranches a couronne
US7127367B2 (en) * 2003-10-27 2006-10-24 Applied Materials, Inc. Tailored temperature uniformity
US20080090309A1 (en) * 2003-10-27 2008-04-17 Ranish Joseph M Controlled annealing method
US8536492B2 (en) * 2003-10-27 2013-09-17 Applied Materials, Inc. Processing multilayer semiconductors with multiple heat sources
JP4826994B2 (ja) * 2004-09-13 2011-11-30 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US7788589B2 (en) * 2004-09-30 2010-08-31 Microsoft Corporation Method and system for improved electronic task flagging and management
JP2008526010A (ja) * 2004-12-28 2008-07-17 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 低いホール密度を有する薄層を得るための方法
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
JP4786925B2 (ja) * 2005-04-04 2011-10-05 東京エレクトロン株式会社 基板処理方法および基板処理装置
US7700376B2 (en) * 2005-04-06 2010-04-20 Applied Materials, Inc. Edge temperature compensation in thermal processing particularly useful for SOI wafers
DE602005009159D1 (de) * 2005-06-10 2008-10-02 Soitec Silicon On Insulator Kalibrierverfahren für Apparaturen zur thermischen Behandlung
FR2895563B1 (fr) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
JP5168788B2 (ja) * 2006-01-23 2013-03-27 信越半導体株式会社 Ｓｏｉウエーハの製造方法
FR2899382B1 (fr) * 2006-03-29 2008-08-22 Soitec Silicon On Insulator Procede de fabrication de structures soi avec limitation des lignes de glissement
EP1918349A1 (de) * 2006-10-12 2008-05-07 SOLVAY (Société Anonyme) LIchtemittierendes Material
US8222574B2 (en) * 2007-01-15 2012-07-17 Applied Materials, Inc. Temperature measurement and control of wafer support in thermal processing chamber
US7860379B2 (en) * 2007-01-15 2010-12-28 Applied Materials, Inc. Temperature measurement and control of wafer support in thermal processing chamber
US8111978B2 (en) * 2008-07-11 2012-02-07 Applied Materials, Inc. Rapid thermal processing chamber with shower head
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
CN102479690B (zh) * 2010-11-23 2013-12-11 中芯国际集成电路制造(上海)有限公司 提高晶圆上源漏极退火时工作电流均匀性的方法
US9814099B2 (en) * 2013-08-02 2017-11-07 Applied Materials, Inc. Substrate support with surface feature for reduced reflection and manufacturing techniques for producing same
WO2017059114A1 (en) * 2015-10-01 2017-04-06 Sunedison Semiconductor Limited Cvd apparatus
CN115910866A (zh) * 2022-12-07 2023-04-04 西安奕斯伟材料科技有限公司 一种外延晶圆的生产控制方法和装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128525A (ja) * 1985-11-29 1987-06-10 Matsushita Electric Ind Co Ltd 化合物半導体基板のアニ−ル方法
KR0155545B1 (ko) * 1988-06-27 1998-12-01 고다까 토시오 기판의 열처리 장치
US5011794A (en) * 1989-05-01 1991-04-30 At&T Bell Laboratories Procedure for rapid thermal annealing of implanted semiconductors
KR100194267B1 (ko) * 1990-01-19 1999-06-15 버킷 이.모리스 반도체 웨이퍼 또는 기판 가열장치 및 방법
JP3563224B2 (ja) * 1996-03-25 2004-09-08 住友電気工業株式会社 半導体ウエハの評価方法、熱処理方法、および熱処理装置
US5937142A (en) * 1996-07-11 1999-08-10 Cvc Products, Inc. Multi-zone illuminator for rapid thermal processing
US6051512A (en) * 1997-04-11 2000-04-18 Steag Rtp Systems Apparatus and method for rapid thermal processing (RTP) of a plurality of semiconductor wafers
US6303411B1 (en) * 1999-05-03 2001-10-16 Vortek Industries Ltd. Spatially resolved temperature measurement and irradiance control
DE19936081A1 (de) * 1999-07-30 2001-02-08 Siemens Ag Vorrichtung und Verfahren zum Temperieren eines Mehrschichtkörpers, sowie ein unter Anwendung des Verfahrens hergestellter Mehrschichtkörper
US7037797B1 (en) * 2000-03-17 2006-05-02 Mattson Technology, Inc. Localized heating and cooling of substrates
KR100789205B1 (ko) * 2000-03-29 2007-12-31 신에쯔 한도타이 가부시키가이샤 실리콘 웨이퍼 및 에스오아이 웨이퍼의 제조방법, 그리고그 에스오아이 웨이퍼
JP2002184961A (ja) * 2000-09-29 2002-06-28 Canon Inc Ｓｏｉ基板の熱処理方法およびｓｏｉ基板
JP2002118071A (ja) * 2000-10-10 2002-04-19 Ushio Inc 光照射式加熱処理装置及び方法
TW540121B (en) * 2000-10-10 2003-07-01 Ushio Electric Inc Heat treatment device and process with light irradiation
FR2846786B1 (fr) * 2002-11-05 2005-06-17 Procede de recuit thermique rapide de tranches a couronne

Also Published As

Publication number Publication date
CN100541739C (zh) 2009-09-16
FR2846787B1 (fr) 2005-12-30
US7049250B2 (en) 2006-05-23
KR100814998B1 (ko) 2008-03-18
EP2330616A3 (de) 2011-12-07
AU2003280109A8 (en) 2004-06-07
CN1711629A (zh) 2005-12-21
JP4772501B2 (ja) 2011-09-14
US20040151483A1 (en) 2004-08-05
AU2003280109A1 (en) 2004-06-07
FR2846786A1 (fr) 2004-05-07
TW200416895A (en) 2004-09-01
EP1559136A2 (de) 2005-08-03
FR2846786B1 (fr) 2005-06-17
JP2006505959A (ja) 2006-02-16
US20050094990A1 (en) 2005-05-05
EP2330616A2 (de) 2011-06-08
US6853802B2 (en) 2005-02-08
EP1559136B1 (de) 2011-10-12
KR20050062653A (ko) 2005-06-23
WO2004042802A3 (en) 2004-08-12
WO2004042802A2 (en) 2004-05-21
FR2846787A1 (fr) 2004-05-07
TWI278937B (en) 2007-04-11

Similar Documents

Publication Publication Date Title
ATE528790T1 (de) Verfahren zum schnellen tempern von mehrschicht- wafern mit einer kante
JP4290068B2 (ja) ウェーハ製造方法
EP2091071B1 (de) Verfahren zum Bonden zweier Substrate
ATE467465T1 (de) Verfahren und maschine zum automatischen inspizieren und sortieren von objekten gemäss ihrer dicke
DE502007003501D1 (de) Nden halbleiterwafers und halbleiterbauelement
TW200507113A (en) Method for treating semiconductor processing components and components formed thereby
WO2006099498A3 (en) Semiconductor wafer metrology apparatus and methods
WO2004057260A3 (en) Heat exchange technique
ATE469438T1 (de) Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche
TWI485760B (zh) 將薄片特別是晶圓從脆材料切離的方法與裝置
TW200727349A (en) Treatment of semiconductor wafers
WO2003100931A3 (en) Methods and systems for identifying and/or removing an oxide-induced zone of defects in a semiconductor device structure
JP2002538624A5 (de)
JP2004214400A5 (de)
JPH07323385A (ja) 脆性材料の割断方法
TW200603350A (en) Bonding apparatus, bonding method, and method for manufacturing semiconductor device
DE69931339D1 (de) Verfahren zur identifikation einer durch einen "heat-soak-test" thermisch behandelten glasscheibe
ATE383057T1 (de) Verfahren zur verlängerung der nützlichen lebensdauer eines molybdänsilizid-heizelement
JPS61183949A (ja) 半導体装置の製造方法
WO2003019637A3 (de) Verfahren zur wärmebehandlung der oberflächenbehandlung eines halbleiters mit hilfe eines laserpulses
JPS566432A (en) Treatment of semiconductor substrate
KR100262529B1 (ko) 반도체 소자의 제조 방법
JPS558067A (en) Manufacture of semiconductor wafer
JPH02189920A (ja) 酸化膜の形成方法及び酸化装置
JPS624316A (ja) 半導体装置のアニ−ル方法

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties