ATE469438T1 - Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche - Google Patents

Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche

Info

Publication number
ATE469438T1
ATE469438T1 AT04769581T AT04769581T ATE469438T1 AT E469438 T1 ATE469438 T1 AT E469438T1 AT 04769581 T AT04769581 T AT 04769581T AT 04769581 T AT04769581 T AT 04769581T AT E469438 T1 ATE469438 T1 AT E469438T1
Authority
AT
Austria
Prior art keywords
wafer
bonded
treatment
transfer method
wafers
Prior art date
Application number
AT04769581T
Other languages
English (en)
Inventor
Sebastien Kerdiles
Christophe Maleville
Fabrice Letertre
Olivier Rayssac
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE469438T1 publication Critical patent/ATE469438T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Pressure Welding/Diffusion-Bonding (AREA)
  • Threshing Machine Elements (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AT04769581T 2004-09-21 2004-09-21 Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche ATE469438T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2004/003275 WO2006032946A1 (en) 2004-09-21 2004-09-21 Transfer method with a treatment of a surface to be bonded

Publications (1)

Publication Number Publication Date
ATE469438T1 true ATE469438T1 (de) 2010-06-15

Family

ID=34959038

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04769581T ATE469438T1 (de) 2004-09-21 2004-09-21 Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche

Country Status (8)

Country Link
US (2) US7615464B2 (de)
EP (2) EP1792337B1 (de)
JP (1) JP5101287B2 (de)
KR (1) KR20120011095A (de)
CN (1) CN101027769B (de)
AT (1) ATE469438T1 (de)
DE (1) DE602004027422D1 (de)
WO (1) WO2006032946A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2865574B1 (fr) * 2004-01-26 2006-04-07 Soitec Silicon On Insulator Procede de fabrication d'un substrat demontable
JP5064692B2 (ja) * 2006-02-09 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
US20070284730A1 (en) * 2006-06-12 2007-12-13 Wei Shi Method, apparatus, and system for thin die thin thermal interface material in integrated circuit packages
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
US20080268617A1 (en) * 2006-08-09 2008-10-30 Applied Materials, Inc. Methods for substrate surface cleaning suitable for fabricating silicon-on-insulator structures
CN101056339B (zh) 2006-11-06 2011-06-08 华为技术有限公司 回铃音与振铃音相互转换的方法、系统及装置
US20100044827A1 (en) * 2008-08-22 2010-02-25 Kinik Company Method for making a substrate structure comprising a film and substrate structure made by same method
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2962141A1 (fr) * 2010-06-30 2012-01-06 Soitec Silicon On Insulator Technologies Procédé de désoxydation d'une structure multicouche a l'acide fluorhydrique
KR102353489B1 (ko) * 2011-01-25 2022-01-19 에베 그룹 에. 탈너 게엠베하 웨이퍼들의 영구적 결합을 위한 방법
US9305865B2 (en) * 2013-10-31 2016-04-05 Micron Technology, Inc. Devices, systems and methods for manufacturing through-substrate vias and front-side structures
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
KR102930829B1 (ko) * 2025-01-23 2026-02-24 포항공과대학교 산학협력단 반도체 부품 제조방법, 박막형 액추에이터 및 박막형 그립퍼

Family Cites Families (22)

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Publication number Priority date Publication date Assignee Title
US5395788A (en) * 1991-03-15 1995-03-07 Shin Etsu Handotai Co., Ltd. Method of producing semiconductor substrate
JP3294934B2 (ja) * 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
EP1018153A1 (de) * 1997-08-29 2000-07-12 Sharon N. Farrens In sito-plasmaverbindungsverfahren für scheiben
JP3412470B2 (ja) * 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
JPH11251207A (ja) * 1998-03-03 1999-09-17 Canon Inc Ｓｏｉ基板及びその製造方法並びにその製造設備
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
EP1039513A3 (de) * 1999-03-26 2008-11-26 Canon Kabushiki Kaisha Verfahren zur Herstellung einer SOI-Scheibe
JP2001015721A (ja) * 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
JP4628580B2 (ja) * 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
ITVI20020143A1 (it) 2002-07-01 2004-01-02 Thomas Bleiner Segnalatore ottico di emergenza
US6995075B1 (en) 2002-07-12 2006-02-07 Silicon Wafer Technologies Process for forming a fragile layer inside of a single crystalline substrate
JP2004063730A (ja) * 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
FR2847076B1 (fr) * 2002-11-07 2005-02-18 Soitec Silicon On Insulator Procede de detachement d'une couche mince a temperature moderee apres co-implantation
US7176108B2 (en) * 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US6911376B2 (en) * 2003-10-01 2005-06-28 Wafermasters Selective heating using flash anneal

Also Published As

Publication number Publication date
US7972939B2 (en) 2011-07-05
JP2008514023A (ja) 2008-05-01
US7615464B2 (en) 2009-11-10
EP2048706A1 (de) 2009-04-15
WO2006032946A1 (en) 2006-03-30
EP2048706B1 (de) 2012-12-12
CN101027769A (zh) 2007-08-29
JP5101287B2 (ja) 2012-12-19
KR20120011095A (ko) 2012-02-06
US20060270187A1 (en) 2006-11-30
EP1792337A1 (de) 2007-06-06
DE602004027422D1 (de) 2010-07-08
EP1792337B1 (de) 2010-05-26
CN101027769B (zh) 2017-06-23
US20100015780A1 (en) 2010-01-21

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