ATE518240T1 - Isolation eines flachen grabens (sti) für vlsi- anwendungen - Google Patents

Isolation eines flachen grabens (sti) für vlsi- anwendungen

Info

Publication number
ATE518240T1
ATE518240T1 AT00101726T AT00101726T ATE518240T1 AT E518240 T1 ATE518240 T1 AT E518240T1 AT 00101726 T AT00101726 T AT 00101726T AT 00101726 T AT00101726 T AT 00101726T AT E518240 T1 ATE518240 T1 AT E518240T1
Authority
AT
Austria
Prior art keywords
trench
oxide layer
depositing
insulating oxide
silicon nitride
Prior art date
Application number
AT00101726T
Other languages
English (en)
Inventor
Herbert Ho
Radhika Srinivasan
Erwin Hammerl
Farid Agahi
Gary Bronner
Bertrand Flietner
Original Assignee
Ibm
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Infineon Technologies Ag filed Critical Ibm
Application granted granted Critical
Publication of ATE518240T1 publication Critical patent/ATE518240T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
AT00101726T 1999-02-05 2000-01-27 Isolation eines flachen grabens (sti) für vlsi- anwendungen ATE518240T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/245,958 US6140208A (en) 1999-02-05 1999-02-05 Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications

Publications (1)

Publication Number Publication Date
ATE518240T1 true ATE518240T1 (de) 2011-08-15

Family

ID=22928798

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00101726T ATE518240T1 (de) 1999-02-05 2000-01-27 Isolation eines flachen grabens (sti) für vlsi- anwendungen

Country Status (6)

Country Link
US (1) US6140208A (de)
EP (1) EP1026734B1 (de)
JP (1) JP3689298B2 (de)
KR (1) KR100420709B1 (de)
AT (1) ATE518240T1 (de)
TW (1) TW469568B (de)

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TW448537B (en) * 1999-10-29 2001-08-01 Taiwan Semiconductor Mfg Manufacturing method of shallow trench isolation
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KR100428804B1 (ko) * 2001-02-23 2004-04-29 삼성전자주식회사 반도체 제조 공정의 막질 형성 방법, 이를 이용한 트렌치 격리 형성 방법 및 그에 따른 소자 분리 트렌치 격리 구조
JP4911826B2 (ja) * 2001-02-27 2012-04-04 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置およびその製造方法
JP2002289683A (ja) * 2001-03-28 2002-10-04 Nec Corp トレンチ分離構造の形成方法および半導体装置
KR100407567B1 (ko) * 2001-04-10 2003-12-01 삼성전자주식회사 덴트 없는 트렌치 격리 형성 방법
DE10222083B4 (de) * 2001-05-18 2010-09-23 Samsung Electronics Co., Ltd., Suwon Isolationsverfahren für eine Halbleitervorrichtung
US6732550B2 (en) * 2001-09-06 2004-05-11 Lightwave Microsystems, Inc. Method for performing a deep trench etch for a planar lightwave circuit
US6426272B1 (en) * 2001-09-24 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to reduce STI HDP-CVD USG deposition induced defects
JP3577024B2 (ja) * 2001-10-09 2004-10-13 エルピーダメモリ株式会社 半導体装置及びその製造方法
KR100493018B1 (ko) * 2002-06-12 2005-06-07 삼성전자주식회사 반도체 장치의 제조방법
KR100461330B1 (ko) * 2002-07-19 2004-12-14 주식회사 하이닉스반도체 반도체 소자의 ｓｔｉ 형성공정
US6825097B2 (en) 2002-08-07 2004-11-30 International Business Machines Corporation Triple oxide fill for trench isolation
KR100443126B1 (ko) * 2002-08-19 2004-08-04 삼성전자주식회사 트렌치 구조물 및 이의 형성 방법
JP2004111547A (ja) * 2002-09-17 2004-04-08 Toshiba Corp 半導体装置、半導体装置の製造方法
US6787409B2 (en) * 2002-11-26 2004-09-07 Mosel Vitelic, Inc. Method of forming trench isolation without grooving
KR100500443B1 (ko) * 2002-12-13 2005-07-12 삼성전자주식회사 리세스된 게이트 전극을 갖는 모스 트랜지스터 및 그제조방법
KR100849361B1 (ko) * 2002-12-28 2008-07-29 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US6867472B2 (en) 2003-01-08 2005-03-15 Infineon Technologies Ag Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization
US6998666B2 (en) * 2004-01-09 2006-02-14 International Business Machines Corporation Nitrided STI liner oxide for reduced corner device impact on vertical device performance
US7015113B2 (en) * 2004-04-01 2006-03-21 Micron Technology, Inc. Methods of forming trench isolation regions
KR100600055B1 (ko) * 2004-06-30 2006-07-13 주식회사 하이닉스반도체 리프팅을 방지한 반도체소자의 소자분리 방법
KR100731103B1 (ko) * 2005-12-29 2007-06-21 동부일렉트로닉스 주식회사 반도체 소자의 격리막 형성방법
KR100764742B1 (ko) 2006-06-16 2007-10-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8012846B2 (en) * 2006-08-04 2011-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures and methods of fabricating isolation structures
US7700488B2 (en) * 2007-01-16 2010-04-20 International Business Machines Corporation Recycling of ion implantation monitor wafers
KR100980058B1 (ko) * 2008-03-27 2010-09-03 주식회사 하이닉스반도체 메모리 소자의 소자분리 구조 및 형성 방법
US8703550B2 (en) 2012-06-18 2014-04-22 International Business Machines Corporation Dual shallow trench isolation liner for preventing electrical shorts
US9059194B2 (en) 2013-01-10 2015-06-16 International Business Machines Corporation High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control
KR102130056B1 (ko) 2013-11-15 2020-07-03 삼성전자주식회사 핀 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
KR102246280B1 (ko) * 2014-03-26 2021-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US9653507B2 (en) 2014-06-25 2017-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench isolation shrinkage method for enhanced device performance
US9754993B2 (en) * 2015-08-31 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolations and methods of forming the same
US10950454B2 (en) * 2017-08-04 2021-03-16 Lam Research Corporation Integrated atomic layer passivation in TCP etch chamber and in-situ etch-ALP method
US11088022B2 (en) 2018-09-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Different isolation liners for different type FinFETs and associated isolation feature fabrication

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US4269654A (en) * 1977-11-18 1981-05-26 Rca Corporation Silicon nitride and silicon oxide etchant
JPS6083346A (ja) * 1983-10-14 1985-05-11 Hitachi Ltd 半導体集積回路装置
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5272104A (en) * 1993-03-11 1993-12-21 Harris Corporation Bonded wafer process incorporating diamond insulator
CA2131668C (en) * 1993-12-23 1999-03-02 Carol Galli Isolation structure using liquid phase oxide deposition
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
US5643823A (en) * 1995-09-21 1997-07-01 Siemens Aktiengesellschaft Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
KR100392828B1 (ko) * 1995-10-13 2003-10-17 램 리서치 코포레이션 브러시를통한화학약품공급방법및장치
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
US5731241A (en) * 1997-05-15 1998-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned sacrificial oxide for shallow trench isolation
US5933749A (en) * 1997-10-27 1999-08-03 United Microelectronics Corp. Method for removing a top corner of a trench

Also Published As

Publication number Publication date
EP1026734B1 (de) 2011-07-27
KR20000057890A (ko) 2000-09-25
JP2000228442A (ja) 2000-08-15
JP3689298B2 (ja) 2005-08-31
US6140208A (en) 2000-10-31
EP1026734A2 (de) 2000-08-09
EP1026734A3 (de) 2001-01-17
TW469568B (en) 2001-12-21
KR100420709B1 (ko) 2004-03-02

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