ATE491207T1 - Gleichzeitige lesung von statusregistern - Google Patents
Gleichzeitige lesung von statusregisternInfo
- Publication number
- ATE491207T1 ATE491207T1 AT07844009T AT07844009T ATE491207T1 AT E491207 T1 ATE491207 T1 AT E491207T1 AT 07844009 T AT07844009 T AT 07844009T AT 07844009 T AT07844009 T AT 07844009T AT E491207 T1 ATE491207 T1 AT E491207T1
- Authority
- AT
- Austria
- Prior art keywords
- subset
- memory device
- memory
- status information
- drive
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- Dram (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
- Communication Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/548,430 US7593279B2 (en) | 2006-10-11 | 2006-10-11 | Concurrent status register read |
| PCT/US2007/080779 WO2008045856A2 (en) | 2006-10-11 | 2007-10-09 | Concurrent reading of status registers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE491207T1 true ATE491207T1 (de) | 2010-12-15 |
Family
ID=39283566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT07844009T ATE491207T1 (de) | 2006-10-11 | 2007-10-09 | Gleichzeitige lesung von statusregistern |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7593279B2 (de) |
| EP (1) | EP2076905B1 (de) |
| JP (3) | JP2010507148A (de) |
| KR (1) | KR101125947B1 (de) |
| CN (1) | CN101523502B (de) |
| AT (1) | ATE491207T1 (de) |
| DE (1) | DE602007011092D1 (de) |
| TW (1) | TW200834598A (de) |
| WO (1) | WO2008045856A2 (de) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9262326B2 (en) * | 2006-08-14 | 2016-02-16 | Qualcomm Incorporated | Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem |
| US7796462B2 (en) | 2007-02-22 | 2010-09-14 | Mosaid Technologies Incorporated | Data flow control in multiple independent port |
| US7809901B2 (en) * | 2007-08-30 | 2010-10-05 | Micron Technology, Inc. | Combined parallel/serial status register read |
| KR100955684B1 (ko) | 2008-10-02 | 2010-05-06 | 주식회사 하이닉스반도체 | 플래그신호 생성회로 및 반도체 메모리 장치 |
| US8180500B2 (en) * | 2009-07-29 | 2012-05-15 | Nanya Technology Corp. | Temperature sensing system and related temperature sensing method |
| WO2011134051A1 (en) * | 2010-04-26 | 2011-11-03 | Mosaid Technologies Incorporated | Serially connected memory having subdivided data interface |
| US9778877B1 (en) * | 2011-11-02 | 2017-10-03 | Rambus Inc. | High capacity, high performance memory system |
| CN104636271B (zh) * | 2011-12-22 | 2018-03-30 | 英特尔公司 | 访问命令/地址寄存器装置中存储的数据 |
| JP2014149669A (ja) * | 2013-01-31 | 2014-08-21 | Toshiba Corp | 半導体記憶装置 |
| JP2015069602A (ja) * | 2013-09-30 | 2015-04-13 | 株式会社東芝 | メモリ・システム |
| US20150213850A1 (en) * | 2014-01-24 | 2015-07-30 | Qualcomm Incorporated | Serial data transmission for dynamic random access memory (dram) interfaces |
| US10223311B2 (en) | 2015-03-30 | 2019-03-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device for sharing inter-memory command and information, memory system including the same and method of operating the memory system |
| JP6753746B2 (ja) * | 2016-09-15 | 2020-09-09 | キオクシア株式会社 | 半導体記憶装置 |
| US10572344B2 (en) * | 2017-04-27 | 2020-02-25 | Texas Instruments Incorporated | Accessing error statistics from DRAM memories having integrated error correction |
| JP6453492B1 (ja) * | 2018-01-09 | 2019-01-16 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
| KR102576766B1 (ko) * | 2018-07-13 | 2023-09-11 | 에스케이하이닉스 주식회사 | 반도체장치 |
| US10878881B1 (en) * | 2019-11-26 | 2020-12-29 | Nanya Technology Corporation | Memory apparatus and refresh method thereof |
| EP4024396B1 (de) * | 2020-09-04 | 2023-12-20 | Changxin Memory Technologies, Inc. | Lese- und schreibverfahren für eine speichervorrichtung und speichervorrichtung |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4363108A (en) * | 1979-06-25 | 1982-12-07 | Honeywell Information Systems Inc. | Low cost programmable video computer terminal |
| US5216672A (en) | 1992-04-24 | 1993-06-01 | Digital Equipment Corporation | Parallel diagnostic mode for testing computer memory |
| US5640521A (en) * | 1992-06-17 | 1997-06-17 | Texas Instruments Incorporated | Addressable shadow port and protocol with remote I/O, contol and interrupt ports |
| JP3579461B2 (ja) * | 1993-10-15 | 2004-10-20 | 株式会社ルネサステクノロジ | データ処理システム及びデータ処理装置 |
| WO1998035296A1 (fr) * | 1997-02-07 | 1998-08-13 | Mitsubishi Denki Kabushiki Kaisha | Controleur de bus et systeme de controle de bus |
| US20010011318A1 (en) | 1997-02-27 | 2001-08-02 | Vishram P. Dalvi | Status indicators for flash memory |
| US6049856A (en) * | 1997-05-27 | 2000-04-11 | Unisys Corporation | System for simultaneously accessing two portions of a shared memory |
| US6279084B1 (en) * | 1997-10-24 | 2001-08-21 | Compaq Computer Corporation | Shadow commands to optimize sequencing of requests in a switch-based multi-processor system |
| US6154816A (en) * | 1997-10-24 | 2000-11-28 | Compaq Computer Corp. | Low occupancy protocol for managing concurrent transactions with dependencies |
| US7024518B2 (en) | 1998-02-13 | 2006-04-04 | Intel Corporation | Dual-port buffer-to-memory interface |
| JP3580702B2 (ja) * | 1998-06-03 | 2004-10-27 | シャープ株式会社 | 不揮発性半導体記憶装置 |
| US5963482A (en) | 1998-07-14 | 1999-10-05 | Winbond Electronics Corp. | Memory integrated circuit with shared read/write line |
| KR100330164B1 (ko) * | 1999-04-27 | 2002-03-28 | 윤종용 | 무효 블록들을 가지는 복수의 플래시 메모리들을 동시에 프로그램하는 방법 |
| JP2001043671A (ja) * | 1999-07-28 | 2001-02-16 | Oki Micro Design Co Ltd | 半導体装置 |
| US20050160218A1 (en) * | 2004-01-20 | 2005-07-21 | Sun-Teck See | Highly integrated mass storage device with an intelligent flash controller |
| US6728798B1 (en) * | 2000-07-28 | 2004-04-27 | Micron Technology, Inc. | Synchronous flash memory with status burst output |
| US6530006B1 (en) * | 2000-09-18 | 2003-03-04 | Intel Corporation | System and method for providing reliable transmission in a buffered memory system |
| US7444575B2 (en) * | 2000-09-21 | 2008-10-28 | Inapac Technology, Inc. | Architecture and method for testing of an integrated circuit device |
| US6665755B2 (en) * | 2000-12-22 | 2003-12-16 | Nortel Networks Limited | External memory engine selectable pipeline architecture |
| US6594748B1 (en) * | 2001-11-09 | 2003-07-15 | Lsi Logic Corporation | Methods and structure for pipelined read return control in a shared RAM controller |
| US6851032B2 (en) | 2002-08-16 | 2005-02-01 | Micron Technology, Inc. | Latency reduction using negative clock edge and read flags |
| US7230876B2 (en) * | 2005-02-14 | 2007-06-12 | Qualcomm Incorporated | Register read for volatile memory |
| US7640392B2 (en) | 2005-06-23 | 2009-12-29 | Qualcomm Incorporated | Non-DRAM indicator and method of accessing data not stored in DRAM array |
| KR20100108697A (ko) * | 2009-03-30 | 2010-10-08 | 삼성전자주식회사 | 데이터 출력 패드들의 스왑 기능을 갖는 반도체 메모리 장치 |
-
2006
- 2006-10-11 US US11/548,430 patent/US7593279B2/en active Active
-
2007
- 2007-10-09 AT AT07844009T patent/ATE491207T1/de not_active IP Right Cessation
- 2007-10-09 DE DE602007011092T patent/DE602007011092D1/de active Active
- 2007-10-09 JP JP2009532528A patent/JP2010507148A/ja not_active Withdrawn
- 2007-10-09 CN CN2007800377720A patent/CN101523502B/zh active Active
- 2007-10-09 WO PCT/US2007/080779 patent/WO2008045856A2/en active Application Filing
- 2007-10-09 EP EP07844009A patent/EP2076905B1/de active Active
- 2007-10-09 KR KR1020097009629A patent/KR101125947B1/ko active IP Right Grant
- 2007-10-11 TW TW096138067A patent/TW200834598A/zh unknown
-
2013
- 2013-06-05 JP JP2013119287A patent/JP5475170B2/ja active Active
-
2014
- 2014-02-20 JP JP2014031055A patent/JP5774739B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2076905B1 (de) | 2010-12-08 |
| JP2013232276A (ja) | 2013-11-14 |
| KR101125947B1 (ko) | 2012-04-12 |
| US20080089138A1 (en) | 2008-04-17 |
| TW200834598A (en) | 2008-08-16 |
| CN101523502A (zh) | 2009-09-02 |
| JP5475170B2 (ja) | 2014-04-16 |
| WO2008045856A3 (en) | 2008-07-24 |
| WO2008045856A2 (en) | 2008-04-17 |
| DE602007011092D1 (de) | 2011-01-20 |
| WO2008045856B1 (en) | 2008-10-02 |
| CN101523502B (zh) | 2012-11-28 |
| KR20090085056A (ko) | 2009-08-06 |
| US7593279B2 (en) | 2009-09-22 |
| JP5774739B2 (ja) | 2015-09-09 |
| EP2076905A2 (de) | 2009-07-08 |
| JP2010507148A (ja) | 2010-03-04 |
| JP2014139798A (ja) | 2014-07-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |