ATE320043T1 - Anschluss mehrerer prozessoren auf externen speicher mit burst mode - Google Patents

Anschluss mehrerer prozessoren auf externen speicher mit burst mode

Info

Publication number
ATE320043T1
ATE320043T1 AT02767643T AT02767643T ATE320043T1 AT E320043 T1 ATE320043 T1 AT E320043T1 AT 02767643 T AT02767643 T AT 02767643T AT 02767643 T AT02767643 T AT 02767643T AT E320043 T1 ATE320043 T1 AT E320043T1
Authority
AT
Austria
Prior art keywords
burst
external memory
burst mode
several processors
connecting several
Prior art date
Application number
AT02767643T
Other languages
English (en)
Inventor
Eugene P Herczog
Melbourn Royston Park
Original Assignee
Ttp Communications Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ttp Communications Ltd filed Critical Ttp Communications Ltd
Application granted granted Critical
Publication of ATE320043T1 publication Critical patent/ATE320043T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
AT02767643T 2001-09-17 2002-09-17 Anschluss mehrerer prozessoren auf externen speicher mit burst mode ATE320043T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0122401.3A GB0122401D0 (en) 2001-09-17 2001-09-17 Interfacing processors with external memory

Publications (1)

Publication Number Publication Date
ATE320043T1 true ATE320043T1 (de) 2006-03-15

Family

ID=9922208

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02767643T ATE320043T1 (de) 2001-09-17 2002-09-17 Anschluss mehrerer prozessoren auf externen speicher mit burst mode

Country Status (10)

Country Link
US (1) US7716442B2 (de)
EP (1) EP1436710B1 (de)
JP (1) JP4322116B2 (de)
KR (1) KR100899514B1 (de)
CN (1) CN1296843C (de)
AT (1) ATE320043T1 (de)
DE (1) DE60209761T2 (de)
ES (1) ES2259718T3 (de)
GB (1) GB0122401D0 (de)
WO (1) WO2003025768A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9876670B2 (en) 2004-07-30 2018-01-23 Commscope Technologies Llc Local network node
WO2006010957A2 (en) 2004-07-30 2006-02-02 Andrew Richardson Signal transmission method from a local network node
US8290527B2 (en) 2004-07-30 2012-10-16 Airvana, Corp. Power control in a local network node (LNN)
US7419038B2 (en) 2005-05-31 2008-09-02 Great Stuff, Inc. Reel and reel housing
JP6053384B2 (ja) * 2012-08-08 2016-12-27 キヤノン株式会社 情報処理装置、メモリ制御装置およびその制御方法
GB2522057B (en) 2014-01-13 2021-02-24 Advanced Risc Mach Ltd A data processing system and method for handling multiple transactions
CN111371526A (zh) * 2020-03-16 2020-07-03 天津津航计算技术研究所 一种用于多任务模块猝发通信条件下的混合多址方法
US12111781B2 (en) * 2022-03-11 2024-10-08 Micron Technology, Inc. Data burst suspend mode using multi-level signaling

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US5093914A (en) * 1989-12-15 1992-03-03 At&T Bell Laboratories Method of controlling the execution of object-oriented programs
US5592435A (en) * 1994-06-03 1997-01-07 Intel Corporation Pipelined read architecture for memory
US5577230A (en) * 1994-08-10 1996-11-19 At&T Corp. Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch
JP3176228B2 (ja) * 1994-08-23 2001-06-11 シャープ株式会社 半導体記憶装置
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
EP0777182B1 (de) * 1995-11-28 2001-07-04 Bull S.A. Speicherzugangsbegrenzer für dynamischen RAM
JP3264614B2 (ja) 1996-01-30 2002-03-11 富士写真光機株式会社 観察装置
US6061346A (en) * 1997-01-17 2000-05-09 Telefonaktiebolaget Lm Ericsson (Publ) Secure access method, and associated apparatus, for accessing a private IP network
KR100245276B1 (ko) * 1997-03-15 2000-02-15 윤종용 버스트 모드 성능을 갖는 랜덤 억세스 메모리 장치 및 그의 동작 방법
JP3728641B2 (ja) * 1997-08-05 2005-12-21 株式会社リコー 画像形成装置
US6216180B1 (en) * 1998-05-21 2001-04-10 Intel Corporation Method and apparatus for a nonvolatile memory interface for burst read operations
JP4060442B2 (ja) 1998-05-28 2008-03-12 富士通株式会社 メモリデバイス
JP3910301B2 (ja) 1998-12-14 2007-04-25 株式会社東芝 半導体装置及びその製造方法
WO2000043897A1 (fr) * 1999-01-20 2000-07-27 Fujitsu Limited Systeme de gestion de fichier comme support de conference
US6457075B1 (en) * 1999-05-17 2002-09-24 Koninkijke Philips Electronics N.V. Synchronous memory system with automatic burst mode switching as a function of the selected bus master
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JP2001014840A (ja) * 1999-06-24 2001-01-19 Nec Corp 複数ラインバッファ型メモリｌｓｉ
EP1226505B1 (de) * 1999-11-05 2005-01-26 Analog Devices, Inc. Architektur und system von einem generischen und seriellen port
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
JP4538911B2 (ja) * 2000-06-19 2010-09-08 ブラザー工業株式会社 メモリアクセス制御装置および記憶媒体
US6278654B1 (en) * 2000-06-30 2001-08-21 Micron Technology, Inc. Active terminate command in synchronous flash memory
DE10107833B4 (de) * 2001-02-16 2012-02-16 Robert Bosch Gmbh Speicheranordnung und Verfahren zum Auslesen einer Speicheranordnung

Also Published As

Publication number Publication date
EP1436710B1 (de) 2006-03-08
EP1436710A1 (de) 2004-07-14
US7716442B2 (en) 2010-05-11
GB0122401D0 (en) 2001-11-07
CN1296843C (zh) 2007-01-24
CN1555528A (zh) 2004-12-15
KR20040045446A (ko) 2004-06-01
KR100899514B1 (ko) 2009-05-27
WO2003025768A1 (en) 2003-03-27
JP4322116B2 (ja) 2009-08-26
US20050005035A1 (en) 2005-01-06
ES2259718T3 (es) 2006-10-16
DE60209761T2 (de) 2006-11-09
JP2005503612A (ja) 2005-02-03
DE60209761D1 (de) 2006-05-04

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Legal Events

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