JP4322116B2 - バーストモードをサポートする外部メモリとプロセッサとのインタフェース方法 - Google Patents
バーストモードをサポートする外部メモリとプロセッサとのインタフェース方法 Download PDFInfo
- Publication number
- JP4322116B2 JP4322116B2 JP2003529329A JP2003529329A JP4322116B2 JP 4322116 B2 JP4322116 B2 JP 4322116B2 JP 2003529329 A JP2003529329 A JP 2003529329A JP 2003529329 A JP2003529329 A JP 2003529329A JP 4322116 B2 JP4322116 B2 JP 4322116B2
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- Japan
- Prior art keywords
- access
- burst mode
- memory
- data device
- data
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Description
び、優先度が高いことによりアクセスM+1で割り込み、その後、アクセスが、N+4およびN+5で再び第1のプロセッサに戻される。このように、アドレス範囲Nのバーストモードの有効利用は、より優先度の高いアドレス範囲Mに対するアクセスによって上手くいかず、アドレス範囲M自体は、アドレスコードMおよびM+1が連続アドレスであるにも関わらずバーストモードを利用することができない。したがって、平均データスループットはかなり損なわれ、あらゆるプロセッサからのあらゆるアクセスに対して最大アクセス時間という最悪の場合に近づく。
Sは、インタフェースIを介してフラッシュメモリFにアクセスを与える際に所定の優先度に従って調整する。バスアービタは、アクセスが与えられているプロセッサを識別し、これがフラッシュメモリデバイスに伝達され、それによってそのプロセッサに、フラッシュメモリ中のデータに対するアクセス用に選択されている特定のブロック読出しレジスタが関連付けられる。したがって、この例では、各ブロック読出しレジスタR1、R2、およびR3を選択して、対応するプロセッサA、B、およびCにフラッシュメモリアクセスを与えることができる。プロセッサの識別は、好ましくは二進符号化され、たとえば、ワードベースのフラッシュデバイスで通常使用されないA[0]アドレス信号を使用することができる。
Claims (8)
- 複数のデータデバイスと、インタフェースを介しての前記複数のデバイス間の外部メモリに対するアクセスの優先度に従ってアクセスを調整する単一のバスアービタとを備えた装置において、前記外部メモリは複数の読出しレジスタを備え、該読出しレジスタはそれぞれ、対応するデータデバイスによるバーストモードアクセスをサポートするように適合され、前記単一のアービタは、アクセスを要求する前記データデバイスの識別に従って初期アクセスバースト後に使用すべき前記読出しレジスタを選択し、前記データデバイスの各々によるバーストモードアクセスのアドレスが、対応する各読出しレジスタに関連付けられることを特徴とする装置。
- 前記データデバイスの識別は不変である、請求項1記載の装置。
- 前記データデバイスの識別はプログラム可能なアドレス範囲に基づく、請求項1記載の装置。
- 前記識別の割り振りは動作要件に基づいて動的に変更される、請求項1記載の装置。
- 前記データデバイスの識別は二進符号化される、請求項1に記載の装置。
- 前記データデバイスはプロセッサまたは直接メモリアクセスモジュールを含む、請求項1に記載の装置。
- 前記メモリはフラッシュメモリまたはRAMメモリを含む、請求項1に記載の装置。
- 各データデバイスによるバーストモードアクセスをサポートするように、単一のバスアービタを介して複数のデータデバイス間の外部メモリに対するアクセスの優先度に従ってアクセスを調整し複数のデータデバイス外部メモリにインタフェースする方法において、前記メモリに複数の読出しレジスタが設けられ、該読出しレジスタはそれぞれ、対応するデータデバイスによるバーストモードアクセスをサポートするために使用され、前記単一のアービタは、アクセスを要求する前記データデバイスの識別に従って初期アクセスバースト後に使用すべき前記読出しレジスタを選択し、前記データデバイスの各々によるバース
トモードアクセスのアドレスが、対応する各読出しレジスタに関連付けられることを特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0122401.3A GB0122401D0 (en) | 2001-09-17 | 2001-09-17 | Interfacing processors with external memory |
GB0122401.3 | 2001-09-17 | ||
PCT/GB2002/004216 WO2003025768A1 (en) | 2001-09-17 | 2002-09-17 | Interfacing processors with external memory supporting burst mode |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005503612A JP2005503612A (ja) | 2005-02-03 |
JP4322116B2 true JP4322116B2 (ja) | 2009-08-26 |
Family
ID=9922208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003529329A Expired - Lifetime JP4322116B2 (ja) | 2001-09-17 | 2002-09-17 | バーストモードをサポートする外部メモリとプロセッサとのインタフェース方法 |
Country Status (10)
Country | Link |
---|---|
US (1) | US7716442B2 (ja) |
EP (1) | EP1436710B1 (ja) |
JP (1) | JP4322116B2 (ja) |
KR (1) | KR100899514B1 (ja) |
CN (1) | CN1296843C (ja) |
AT (1) | ATE320043T1 (ja) |
DE (1) | DE60209761T2 (ja) |
ES (1) | ES2259718T3 (ja) |
GB (1) | GB0122401D0 (ja) |
WO (1) | WO2003025768A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8201673B2 (en) | 2005-05-31 | 2012-06-19 | Great Stuff, Inc. | Temperature control system for electrical cord reel |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1779625B1 (en) | 2004-07-30 | 2018-10-17 | CommScope Technologies LLC | A local network node |
EP1782551B1 (en) | 2004-07-30 | 2016-10-05 | CommScope Technologies LLC | Power control in a local network node (lnn) |
WO2006010957A2 (en) | 2004-07-30 | 2006-02-02 | Andrew Richardson | Signal transmission method from a local network node |
JP6053384B2 (ja) * | 2012-08-08 | 2016-12-27 | キヤノン株式会社 | 情報処理装置、メモリ制御装置およびその制御方法 |
GB2522057B (en) | 2014-01-13 | 2021-02-24 | Advanced Risc Mach Ltd | A data processing system and method for handling multiple transactions |
CN111371526A (zh) * | 2020-03-16 | 2020-07-03 | 天津津航计算技术研究所 | 一种用于多任务模块猝发通信条件下的混合多址方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5093914A (en) * | 1989-12-15 | 1992-03-03 | At&T Bell Laboratories | Method of controlling the execution of object-oriented programs |
US5592435A (en) * | 1994-06-03 | 1997-01-07 | Intel Corporation | Pipelined read architecture for memory |
US5577230A (en) * | 1994-08-10 | 1996-11-19 | At&T Corp. | Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch |
JP3176228B2 (ja) * | 1994-08-23 | 2001-06-11 | シャープ株式会社 | 半導体記憶装置 |
US5878240A (en) * | 1995-05-11 | 1999-03-02 | Lucent Technologies, Inc. | System and method for providing high speed memory access in a multiprocessor, multimemory environment |
EP0777182B1 (en) * | 1995-11-28 | 2001-07-04 | Bull S.A. | A memory access limiter for random access dynamic memories |
JP3264614B2 (ja) | 1996-01-30 | 2002-03-11 | 富士写真光機株式会社 | 観察装置 |
US6061346A (en) * | 1997-01-17 | 2000-05-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Secure access method, and associated apparatus, for accessing a private IP network |
KR100245276B1 (ko) * | 1997-03-15 | 2000-02-15 | 윤종용 | 버스트 모드 성능을 갖는 랜덤 억세스 메모리 장치 및 그의 동작 방법 |
JP3728641B2 (ja) * | 1997-08-05 | 2005-12-21 | 株式会社リコー | 画像形成装置 |
US6216180B1 (en) * | 1998-05-21 | 2001-04-10 | Intel Corporation | Method and apparatus for a nonvolatile memory interface for burst read operations |
JP4060442B2 (ja) | 1998-05-28 | 2008-03-12 | 富士通株式会社 | メモリデバイス |
JP3910301B2 (ja) | 1998-12-14 | 2007-04-25 | 株式会社東芝 | 半導体装置及びその製造方法 |
WO2000043897A1 (fr) * | 1999-01-20 | 2000-07-27 | Fujitsu Limited | Systeme de gestion de fichier comme support de conference |
US6457075B1 (en) * | 1999-05-17 | 2002-09-24 | Koninkijke Philips Electronics N.V. | Synchronous memory system with automatic burst mode switching as a function of the selected bus master |
US6460133B1 (en) * | 1999-05-20 | 2002-10-01 | International Business Machines Corporation | Queue resource tracking in a multiprocessor system |
JP2001014840A (ja) * | 1999-06-24 | 2001-01-19 | Nec Corp | 複数ラインバッファ型メモリlsi |
DE60017775T2 (de) * | 1999-11-05 | 2006-01-12 | Analog Devices Inc., Norwood | Architektur und system von einem generischen und seriellen port |
US6621761B2 (en) * | 2000-05-31 | 2003-09-16 | Advanced Micro Devices, Inc. | Burst architecture for a flash memory |
JP4538911B2 (ja) * | 2000-06-19 | 2010-09-08 | ブラザー工業株式会社 | メモリアクセス制御装置および記憶媒体 |
US6278654B1 (en) * | 2000-06-30 | 2001-08-21 | Micron Technology, Inc. | Active terminate command in synchronous flash memory |
DE10107833B4 (de) * | 2001-02-16 | 2012-02-16 | Robert Bosch Gmbh | Speicheranordnung und Verfahren zum Auslesen einer Speicheranordnung |
-
2001
- 2001-09-17 GB GBGB0122401.3A patent/GB0122401D0/en not_active Ceased
-
2002
- 2002-09-17 CN CNB028181581A patent/CN1296843C/zh not_active Expired - Lifetime
- 2002-09-17 EP EP02767643A patent/EP1436710B1/en not_active Expired - Lifetime
- 2002-09-17 US US10/489,800 patent/US7716442B2/en not_active Expired - Lifetime
- 2002-09-17 ES ES02767643T patent/ES2259718T3/es not_active Expired - Lifetime
- 2002-09-17 DE DE60209761T patent/DE60209761T2/de not_active Expired - Lifetime
- 2002-09-17 AT AT02767643T patent/ATE320043T1/de not_active IP Right Cessation
- 2002-09-17 KR KR1020047003928A patent/KR100899514B1/ko active IP Right Grant
- 2002-09-17 WO PCT/GB2002/004216 patent/WO2003025768A1/en active IP Right Grant
- 2002-09-17 JP JP2003529329A patent/JP4322116B2/ja not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8201673B2 (en) | 2005-05-31 | 2012-06-19 | Great Stuff, Inc. | Temperature control system for electrical cord reel |
Also Published As
Publication number | Publication date |
---|---|
US7716442B2 (en) | 2010-05-11 |
ATE320043T1 (de) | 2006-03-15 |
JP2005503612A (ja) | 2005-02-03 |
EP1436710B1 (en) | 2006-03-08 |
KR100899514B1 (ko) | 2009-05-27 |
CN1296843C (zh) | 2007-01-24 |
KR20040045446A (ko) | 2004-06-01 |
CN1555528A (zh) | 2004-12-15 |
US20050005035A1 (en) | 2005-01-06 |
ES2259718T3 (es) | 2006-10-16 |
WO2003025768A1 (en) | 2003-03-27 |
EP1436710A1 (en) | 2004-07-14 |
GB0122401D0 (en) | 2001-11-07 |
DE60209761D1 (de) | 2006-05-04 |
DE60209761T2 (de) | 2006-11-09 |
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