TW200721164A - Semiconductor memory device with advanced refresh control - Google Patents

Semiconductor memory device with advanced refresh control

Info

Publication number
TW200721164A
TW200721164A TW095136277A TW95136277A TW200721164A TW 200721164 A TW200721164 A TW 200721164A TW 095136277 A TW095136277 A TW 095136277A TW 95136277 A TW95136277 A TW 95136277A TW 200721164 A TW200721164 A TW 200721164A
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
bank
refresh control
refresh
Prior art date
Application number
TW095136277A
Other languages
Chinese (zh)
Other versions
TWI313002B (en
Inventor
Jee-Yul Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200721164A publication Critical patent/TW200721164A/en
Application granted granted Critical
Publication of TWI313002B publication Critical patent/TWI313002B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank; and a bank refresh block for supporting a refresh operation performed in sequence to each bank in response to the refresh information of each bank.
TW095136277A 2005-09-29 2006-09-29 Semiconductor memory device with advanced refresh control TWI313002B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090942 2005-09-29
KR1020060049139A KR100798772B1 (en) 2005-09-29 2006-05-31 Semiconductor memory device

Publications (2)

Publication Number Publication Date
TW200721164A true TW200721164A (en) 2007-06-01
TWI313002B TWI313002B (en) 2009-08-01

Family

ID=38158773

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136277A TWI313002B (en) 2005-09-29 2006-09-29 Semiconductor memory device with advanced refresh control

Country Status (2)

Country Link
KR (1) KR100798772B1 (en)
TW (1) TWI313002B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110004165A (en) 2009-07-07 2011-01-13 삼성전자주식회사 Multi-channel semiconductor memory device for reducing refresh peak current and refresh method thereof
KR101185553B1 (en) * 2009-12-29 2012-09-24 에스케이하이닉스 주식회사 Internal voltage control circuit
KR20120012056A (en) 2010-07-30 2012-02-09 주식회사 하이닉스반도체 Memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355226B1 (en) * 1999-01-12 2002-10-11 삼성전자 주식회사 DRAM performable selectively self-refresh operation for memory bank
JP2002373489A (en) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp Semiconductor memory
JP2003338177A (en) * 2002-05-22 2003-11-28 Mitsubishi Electric Corp Semiconductor memory device
KR100474551B1 (en) * 2003-02-10 2005-03-10 주식회사 하이닉스반도체 Self refresh apparatus and method

Also Published As

Publication number Publication date
KR20070036646A (en) 2007-04-03
TWI313002B (en) 2009-08-01
KR100798772B1 (en) 2008-01-29

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees