KR100798772B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for reducing peak current consumption during a refresh operation of a low power semiconductor memory device having a plurality of banks. A semiconductor including an extended mode register set (EMRS) section including refresh information for each bank and a bank refresh section for supporting sequential refresh operations for each unit bank during refresh operations of at least two banks in response to refresh information for at least two banks. Provide a memory device.

Partial array refresh code, refresh, bank, cell refresh, semiconductor memory device.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram illustrating a semiconductor memory device capable of performing a general file refresh operation.

FIG. 2 is a circuit diagram illustrating a cell refresh enable signal generator of FIG. 1 according to the related art. FIG.

3A to 3D are circuit diagrams illustrating the cell refresh enable signal generation unit of FIG. 1 according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a refresh operation of a semiconductor memory device.

DRAM, a typical semiconductor memory device, needs to be refreshed to prevent data loss of a cell. In particular, portable devices such as laptops and personal digital assistants (PDAs) require low power consumption. Therefore, it is important to reduce the operating current so that data can be stored in the standby state.

DRAMs used in such low-power portable devices perform most of the cell refresh operations to preserve data in a standby state.

However, the general cell refresh operation enables a plurality of banks composed of memory cells at the same time, which causes a lot of peak currents, resulting in problems. Recently, in order to reduce such peak power consumption, refreshing all banks is performed sequentially in the refresh operation for all banks, and in the refresh operation of some banks, a file refresh (piled refresh) is performed to bundle and refresh some selected banks. To perform.

1 is a block diagram illustrating a semiconductor memory device capable of performing a general file refresh operation. At this time, it is assumed that the semiconductor memory device has a 4-bank structure.

Referring to FIG. 1, a semiconductor memory device capable of performing a file refresh operation includes a cell refresh period signal generator 101 that outputs a cell refresh period signal srefreq in response to a cell refresh source signal sref, and an address signal add < In response to 0: 2>), a partial array self refresh code having information of a bank to be refreshed among a plurality of banks is selected to select a bank selection signal (bk <0: 3>) and selected bank information. Extended mode register set (EMRS) section 103 for outputting a signal, cell refresh enable sequentially activated according to four different delay information corresponding to four banks in response to the cell refresh cycle signal srefreq Generates a signal (sefact <0: 3>) and refreshes all or some banks in response to the cell refresh enable signal (sefact <0: 3>) and the selected bank information signal (code <0: 7>). To self-fresh which matches The cell refresh enable signal generation unit 105 that generates the enable signal sefact <0: 3>, and the cell refresh enable signal sefact <0: 3> and the bank selection signal bk <0: 3>. In response, a bank refresh unit 107 selects a bank to be refreshed and performs a refresh operation.

Here, the partial array refresh code is shown in Table 1.

Table 1

First address signal add <0> Second address signal add <1> Third address signal add <2> Bank to refresh code <0: 7>) 0 0 0 Banks 0, 1, 2, 3 0 0 0 One 0, 1 bank One 0 One 0 0 bank 2 0 One One reserved 3 One 0 0 1, 2, 3 banks 4 One 0 One 2, 3 banks 5 One One 0 3 bank 6 One One One reserved 7

Next, a brief operation will be described. A cell refresh cycle signal srefreq is generated in response to the cell refresh source signal sref generated by the refresh command. The bank to be refreshed is selected by the address signal add <0: 2> among the PASR code values set in advance for the file refresh operation. This is output by the bank selection signal (bk <0: 3>) and the selected bank information signal (code <0: 7>). Among the selected bank information signals (code <0: 7>), all banks to be refreshed are selected. Only the bank refresh operation or the partial bank refresh operation is determined and transmitted to the cell refresh enable signal generator 105. That is, only the first selected bank information signal code <0> of the partial array refresh code values shown in Table 1 is transmitted to the cell refresh enable signal generation unit 105.

Thereafter, the cell refresh enable signal generation unit 105 generates a cell refresh enable signal sefact <0: 3> that is sequentially activated in response to the cell refresh cycle signal srefreq. The generated cell refresh enable signals sefact <0: 3> are sequentially activated in the case of all bank refresh operations in response to the first selected bank information signal code <0>. Delivered. In the case of a partial bank refresh operation, the cell refresh enable signals sefact <0: 3> are simultaneously activated and transmitted to the bank refresh unit 107.

Thereafter, four banks are selected by the bank selection signals bk <0: 3>, and the banks selected by the cell refresh enable signals sefact <0: 3> are refreshed.

A circuit diagram of the cell refresh enable signal generation unit 105 guaranteeing such an operation is as follows.

2 is a circuit diagram illustrating the cell refresh enable signal generation unit 105 of FIG. 1 according to the related art. A description will be given on the assumption that the semiconductor memory device has a 4-bank structure as in FIG. 1.

Referring to FIG. 2, the cell refresh enable signal generator 105 includes a predetermined number of NAND gates NAND11 to 19, an inverter INV5 to 13, and a delay circuit (first to third delay circuits).

The cell refresh enable signal generator 105 includes the cell refresh cycle signal srefreq as a basic signal, and the first selected bank information signal code <0> as a control signal. (sefact <0>), a second cell refresh enable signal (sefact <1>), a third cell refresh enable signal (sefact <2>), and a fourth cell refresh enable signal (sefact <3>) are generated. do.

Here, when the first selected bank information signal code <0> is activated (where activation means that a refresh operation should be performed for all banks), the first cell refresh enable signal sefact <0> is generated. It is activated first. Thereafter, the first cell refresh enable signal sefact <0> is delayed by the delay time information of the first delay circuit to activate the second cell refresh enable signal sefact <1>, and then the second cell refresh enable signal sefact <0> is activated. The enable signal sefact <1> is delayed by the delay time information of the second delay circuit so that the third cell refresh enable signal sefact <2> is activated, and then the third cell refresh enable signal sefact < 2>) is delayed by the delay time information of the third delay circuit to activate the fourth cell refresh enable signal "sefact <3>.

When the first selected bank information signal code <0> is deactivated (in which the deactivation means that a refresh operation must be performed for some banks), the first cell refresh enable signal sefact <0> is accordingly performed. ), The second cell refresh enable signal sefact <1>, the third cell refresh enable signal sefact <2> and the fourth cell refresh enable signal sefact <3> are simultaneously activated.

As a result, the cell refresh enable signals sefact <0: 3> are sequentially activated or simultaneously activated according to the activation or deactivation of the first selected bank information signal code <0>.

The cell refresh enable signal (sefact <0: 3>) enables the file refresh operation, thereby reducing the peak current during the refresh operation.

However, in semiconductor memory devices, which require increasingly low power, it is also a waste of peak current to simultaneously refresh some selected banks, although not all banks.

For example, when the fifth selected bank information signal code <4> is selected among the partial array refresh codes, the peak current is wasted because three banks among the four banks are simultaneously refreshed.

Therefore, it is necessary to reduce the peak current during the refresh operation of a low power semiconductor memory device having a plurality of banks.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and a first object of the present invention is to provide a semiconductor memory device that reduces peak current during a refresh operation of a low power semiconductor memory device having a plurality of banks. do.

A second object of the present invention is to provide a semiconductor memory device which sequentially performs refresh operations for each bank during a refresh operation of a low power semiconductor memory device having a plurality of banks.

According to an aspect of the present invention for achieving the above technical problem, a unit bank during a refresh operation of at least two banks in response to a plurality of banks, an EMRS unit containing the refresh information for each bank and the refresh information for each bank Provided is a semiconductor memory device including a bank refresh unit for supporting sequential refresh operations.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3D are circuit diagrams illustrating the cell refresh enable signal generation unit 105 of FIG. 1 according to the present invention. A description will be given on the assumption that the semiconductor memory device has a 4-bank structure as in FIG. 1.

3A to 3D, the cell refresh enable signal generator 105 selectively receives an 8-bit selected bank information signal code <0: 7> and includes a number corresponding to a 4-bank structure. Four decoders. Each decoder selectively receives the refresh activation signals active <0: 3> that are sequentially activated to ensure sequential refresh operations for each bank.

First, referring to FIG. 3A, as a first decoder for generating a first cell refresh enable signal sefact <0> for refreshing a first bank, a first selected bank information signal code <0>, The first NOR gate NOR1 receiving the second selected bank information signal code <1>, the third selected bank information signal code <2>, the first refresh activation signal active <0> and the first The second NOR gate NOR2 outputs the output signal of the NOR gate NOR1 as a first cell refresh enable signal sefact <0>.

3B, the first inverter INV1, the first refresh activation signal active <0>, and the first inverter, which inverts the fifth selected bank information signal code <4>, are used as the second decoder. Third NOR to input the fifth NOR gate NOR5 to which the output signal of INV1 is input, the first selected bank information signal code <0>, and the second selected bank information signal code <1>. The output signals of the fourth NOR gate NOR4 and the fourth NOR gate NOR4, which input the output signals of the gate NOR3, the second refresh activation signal actvie <1>, and the third NOR gate NOR3; The sixth NOR gate NOR6 outputting the output signal of the fifth NOR gate NOR5 as a second cell refresh enable signal sefact <1> may be implemented.

3C, the fourth inverter INV4, the first refresh activation signal active <0>, and the fourth inverter, which inverts the sixth selected bank information signal code <5>, are used as a third decoder. A ninth NOR gate NOR9 for inputting the output signal of INV4, a third inverter INV3 for inverting the fifth selected bank information signal code <4>, and a second refresh activation signal active <1>. ) And an eighth NOR gate NOR for inputting the output signal of the third inverter INV3, the second inverter INV2 and the third refresh activation signal inverting the first selected bank information signal code <0>. Outputs of the seventh NOR gate NOR7, the seventh NOR gate NOR7, the eighth NOR gate NOR8, and the ninth NOR gate NOR9 which input (active <2>) and the second inverter INV2. A tenth NOR gate NOR10 outputting the signal as a third cell refresh enable signal sefact <2> may be implemented.

In addition, referring to FIG. 3D, an eighth inverter INV8, a first refresh activation signal active <0>, and an eighth inverter, which inverts the seventh selected bank information signal code <6>, may be used as a fourth decoder. Fourteenth NOR gate (NOR14) for inputting the output signal of INV8, the seventh inverter (INV7) for inverting the sixth selected bank information signal (code <5>), and the second refresh activation signal (active <1>). ) And the 13th NOR gate (NOR13) which inputs the output signal of the 7th inverter (INV7), the 6th inverter (INV6) and the 3rd refresh activation signal which invert the 5th selected bank information signal (code <4>). a twelfth NOR gate NOR12 for inputting the active signal 212 and the output signal of the sixth inverter INV6, the fifth inverter INV5 for inverting the first selected bank information signal code <0>, The eleventh NOR gate NOR11, the eleventh NOR gate NOR11, and the twelfth NOR gate NOR12 that input the fourth refresh activation signal active <3> and the output signal of the fifth inverter INV5. 13 can be implemented as a NOR gate (NOR13) and a NOR gate 14. The NOR gate 15 (NOR15) using as input a (NOR14) for outputting a fourth self-refresh enable signal (NOR15).

For example, the cell refresh enable signal sefact <0: 3> is generated based on the first to fourth decoders. First, the cell refresh cycle signal generation unit 101 performs a cell refresh cycle signal srefreq. Outputs the signal to the cell refresh enable signal generation unit 105, and selects the fifth selected bank information signal code <4> from the EMRS unit 103 to the cell refresh enable signal generation unit 105 in the same manner. To pass.

The cell refresh enable signal generation unit 105 itself generates a refresh activation signal active <0: 3> in order to sequentially refresh each bank. The refresh activation signals active <0: 3> are activated individually and sequentially with certain delay information.

A first signal is input to the first decoder in a state in which a bank (second bank, third bank, and fourth bank) to be refreshed is selected by the fifth selected bank information signal code <4>. The selected bank information signal code <0> is at a logic level high, the second selected bank information signal code <1> is at a logic level high, and the third selected bank information signal code <2> is at a logic level low. As you level each. Here, the factor for determining the logic level of the selected bank information signal code <0: 2> is due to the fifth selected bank information signal code <4> output from the EMRS unit 103. That is, the first selected bank information signal, which is a signal input to the first decoder while the fifth selected bank information signal code <4> has refresh information for the second bank, the third bank, and the fourth bank, code <0>), a refresh of a duplicate bank among the refresh information (see Table 1) of the banks contained in the second selected bank information signal code <1> and the third selected bank information signal code <2>. If there is information, it is level shifted to logic level high, otherwise to logic level low. For example, since the second selected bank information signal code <1> has refresh information for the first bank and the second bank compared to the fifth selected bank information signal code <4>, the logic level is high. The third selected bank information signal code <2> has a refresh information for the first bank, so that the logic level transitions to low.

Therefore, the first refresh enable signal active <0> and the selected bank information signals code <0: 2> that are logic level high are combined to form the first cell refresh enable signal sefact <0>. The level goes low.

Therefore, the bank (refresh information) not included in the fifth selected bank information signal code <4> output from the EMRS unit 103 does not perform the refresh operation.

In the same concept, the second decoder combines the fifth selected bank information signal code <4> to the logic level high and the first refresh activation signal active <0> whose logic level is high.

Subsequently, the first selected bank information signal code <0> and the second selected bank information signal code <1> are transitioned to a logic level high, and in the activation period of the first refresh activation signal active <0>. It is combined with a second refresh activation signal active <1> which is activated by being delayed by a predetermined time. This means that the second cell refresh enable signal sefact <1> is generated after the first cell refresh enable signal sefact <0> is generated.

Hereinafter, since the third decoder and the fourth decoder are the same principle, description thereof will be omitted.

As described above, in the related art, it is determined whether the refresh operation of a bank is for all banks, and in the case of all bank refresh operations, the refresh operation is supported for each bank to reduce peak current consumption, and in the case of some bank refresh operations. In the present invention, the peak current is consumed by supporting the refresh operation of some banks at a time. In the present invention, even when the refresh operation of the bank is all banks or some banks, sequential refresh operations are supported for each bank to reduce the peak current consumption. .

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, since the type and arrangement of the logic used in the above-described embodiment is implemented as an example in which both the input signal and the output signal are high active signals, the implementation of the logic may also change when the active polarity of the signal is changed. There is no such embodiment, because the number of cases is too large, and the change in the embodiment is a matter that can be easily technically inferred by those skilled in the art of the present invention belongs directly to each case I will not mention it.

In addition, in the above-described embodiment, the decoder of the cell refresh enable signal generator should be provided with a number corresponding to the number of banks, and the decoder has been described as an example of implementing a series of circuits. It's just an example.

As described above, the present invention supports a sequential refresh operation for each bank even when the refresh operation of the bank is all banks or some banks, thereby reducing the consumption of peak current.

Therefore, it is possible to ensure the stability and reliability of the semiconductor memory device driven at low power.

Claims (9)

A plurality of banks; An extended mode register set (EMRS) unit including refresh information for each bank; And In response to the refresh information for each bank, a bank refresh unit for supporting a sequential refresh operation for each unit bank during the refresh operation of at least two banks Semiconductor memory device comprising a. The method of claim 1, And the extended mode register set (EMRS) portion includes a partial array prefresh code. The method of claim 2, And the extended mode register set (EMRS) unit outputs a selected bank information signal indicating the partial array refresh code value and a bank selection signal for selecting a bank according to the partial array refresh code value. The method of claim 3, The bank refresh unit, A refresh cycle signal generation unit configured to generate a refresh cycle signal in response to a refresh command; A refresh enable signal generator configured to generate a refresh enable signal sequentially activated in response to the refresh cycle signal and the selected bank information signal; And And a bank selector configured to transfer the refresh enable signal to a bank to be refreshed in response to the bank select signal. The method of claim 4, wherein The refresh enable signal generation unit comprises four decoders. The method of claim 5, The first decoder of the four decoders, A first NOR gate configured to receive a first selected bank information signal, a second selected bank information signal, and a third selected bank information signal; And A semiconductor memory device comprising: a first refresh enable signal activated to generate a refresh enable signal; and a second nor gate configured to output the first refresh enable signal as an input of an output signal of the first nor gate; . The method of claim 6, A second decoder of the four decoders, A first inverter for inverting the fifth selected bank information signal; A fifth NOR gate configured to receive the first refresh activation signal and the output signal of the first inverter; A third NOR gate configured to receive the first selected bank information signal and the second selected bank information signal; A fourth NOR gate having an input of a second refresh activation signal and an output signal of a third NOR gate activated after the activation period of the first refresh activation signal ends; And And a sixth north gate configured to output an output signal of the fourth nor gate and an output signal of the fifth nor gate as a second refresh enable signal. The method of claim 7, wherein As a third decoder of the four decoders, A fourth inverter for inverting the sixth selected bank information signal; A ninth NOR gate configured to receive the first refresh activation signal and the output signal of the fourth inverter; A third inverter for inverting the fifth selected bank information signal; An eighth gate configured to input the second refresh activation signal and the output signal of the third inverter; A second inverter for inverting the first selected bank information signal; A seventh NOR gate configured to receive a third refresh activation signal and an output signal of a second inverter, which are activated after the activation period of the second refresh activation signal ends; And And a tenth north gate configured to output an output signal of the seventh, eighth, and ninth gates as a third refresh enable signal. The method of claim 8, The fourth decoder of the four decoders, An eighth inverter for inverting the seventh selected bank information signal; A fourteenth NOR gate receiving the first refresh activation signal and an output signal of an eighth inverter; A seventh inverter for inverting the sixth selected bank information signal; A thirteenth NOR gate configured to receive the second refresh activation signal and the output signal of the seventh inverter; A sixth inverter for inverting the fifth selected bank information signal; A twelfth NOR gate configured to receive the third refresh activation signal and the output signal of the sixth inverter; A fifth inverter for inverting the first selected bank information signal; An eleventh NOR gate configured as an input of a fourth refresh activation signal and an output signal of a fifth inverter that are activated after the activation period of the third refresh activation signal ends; And And a fifteenth gate configured to input the eleventh NOR gate, the twelfth NOR gate, the thirteenth NOR gate, and the fourteen NOR gate as a fourth refresh enable signal.

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