ATE430365T1 - Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen - Google Patents

Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen

Info

Publication number
ATE430365T1
ATE430365T1 AT04733411T AT04733411T ATE430365T1 AT E430365 T1 ATE430365 T1 AT E430365T1 AT 04733411 T AT04733411 T AT 04733411T AT 04733411 T AT04733411 T AT 04733411T AT E430365 T1 ATE430365 T1 AT E430365T1
Authority
AT
Austria
Prior art keywords
same
cluster
rows
tested
remains
Prior art date
Application number
AT04733411T
Other languages
English (en)
Inventor
Mohamed Azimane
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE430365T1 publication Critical patent/ATE430365T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT04733411T 2003-05-22 2004-05-17 Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen ATE430365T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03101470 2003-05-22
PCT/IB2004/050708 WO2004105045A1 (en) 2003-05-22 2004-05-17 Test of ram address decoder for resistive open defects

Publications (1)

Publication Number Publication Date
ATE430365T1 true ATE430365T1 (de) 2009-05-15

Family

ID=33462201

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04733411T ATE430365T1 (de) 2003-05-22 2004-05-17 Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen

Country Status (9)

Country Link
US (1) US7689878B2 (de)
EP (1) EP1629506B1 (de)
JP (1) JP2007505440A (de)
KR (1) KR20060019553A (de)
CN (1) CN1791943B (de)
AT (1) ATE430365T1 (de)
DE (1) DE602004020887D1 (de)
TW (1) TW200511323A (de)
WO (1) WO2004105045A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7536610B2 (en) * 2004-03-26 2009-05-19 Koninklijke Philips Electronics N.V. Method for detecting resistive-open defects in semiconductor memories
JP4717027B2 (ja) * 2006-05-02 2011-07-06 富士通株式会社 半導体集積回路、テストデータ生成装置およびｌｓｉ試験装置
JP5035663B2 (ja) * 2006-11-06 2012-09-26 独立行政法人科学技術振興機構 診断装置、診断方法、その診断方法をコンピュータに実行させることが可能なプログラム、及びそのプログラムを記録した記録媒体
US8516315B2 (en) * 2010-09-03 2013-08-20 Stmicroelectronics International N.V. Testing of non stuck-at faults in memory
KR101811281B1 (ko) * 2017-04-17 2017-12-22 고려대학교 산학협력단 층 교차 기반 3차원 터보 곱 코드의 복호 방법 및 그 장치

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4335459A (en) * 1980-05-20 1982-06-15 Miller Richard L Single chip random access memory with increased yield and reliability
US4872168A (en) * 1986-10-02 1989-10-03 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit with memory self-test
US5270975A (en) * 1990-03-29 1993-12-14 Texas Instruments Incorporated Memory device having a non-uniform redundancy decoder arrangement
US5392247A (en) * 1991-09-19 1995-02-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including redundancy circuit
WO1996015536A1 (en) * 1994-11-09 1996-05-23 Philips Electronics N.V. A method of testing a memory address decoder and a fault-tolerant memory address decoder
TW312763B (de) * 1995-04-05 1997-08-11 Siemens Ag
US6079037A (en) * 1997-08-20 2000-06-20 Micron Technology, Inc. Method and apparatus for detecting intercell defects in a memory device
JP3246449B2 (ja) * 1998-08-27 2002-01-15 日本電気株式会社 Ｒｏｍ内蔵マイコンのｒｏｍテスト回路
JP3821621B2 (ja) * 1999-11-09 2006-09-13 株式会社東芝 半導体集積回路
JP3866478B2 (ja) * 2000-03-28 2007-01-10 株式会社東芝 半導体集積回路
US6442085B1 (en) * 2000-10-02 2002-08-27 International Business Machines Corporation Self-Test pattern to detect stuck open faults
JP2002358797A (ja) * 2001-05-31 2002-12-13 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
CN1791943B (zh) 2011-08-17
US7689878B2 (en) 2010-03-30
US20070033453A1 (en) 2007-02-08
JP2007505440A (ja) 2007-03-08
TW200511323A (en) 2005-03-16
CN1791943A (zh) 2006-06-21
DE602004020887D1 (de) 2009-06-10
WO2004105045A1 (en) 2004-12-02
KR20060019553A (ko) 2006-03-03
EP1629506B1 (de) 2009-04-29
EP1629506A1 (de) 2006-03-01

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