ATE544157T1 - Verifizierungsoperation für nichtflüchtige speicherung unter verwendung verschiedener spannungen - Google Patents

Verifizierungsoperation für nichtflüchtige speicherung unter verwendung verschiedener spannungen

Info

Publication number
ATE544157T1
ATE544157T1 AT07797703T AT07797703T ATE544157T1 AT E544157 T1 ATE544157 T1 AT E544157T1 AT 07797703 T AT07797703 T AT 07797703T AT 07797703 T AT07797703 T AT 07797703T AT E544157 T1 ATE544157 T1 AT E544157T1
Authority
AT
Austria
Prior art keywords
volatile storage
voltage
verification operation
various voltage
programming
Prior art date
Application number
AT07797703T
Other languages
English (en)
Inventor
Gerrit Hemink
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/421,667 external-priority patent/US7440331B2/en
Priority claimed from US11/421,682 external-priority patent/US7457163B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Application granted granted Critical
Publication of ATE544157T1 publication Critical patent/ATE544157T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AT07797703T 2006-06-01 2007-05-23 Verifizierungsoperation für nichtflüchtige speicherung unter verwendung verschiedener spannungen ATE544157T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/421,667 US7440331B2 (en) 2006-06-01 2006-06-01 Verify operation for non-volatile storage using different voltages
US11/421,682 US7457163B2 (en) 2006-06-01 2006-06-01 System for verifying non-volatile storage using different voltages
PCT/US2007/069589 WO2007143398A2 (en) 2006-06-01 2007-05-23 Verify operation for non-volatile storage using different voltages

Publications (1)

Publication Number Publication Date
ATE544157T1 true ATE544157T1 (de) 2012-02-15

Family

ID=38802196

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07797703T ATE544157T1 (de) 2006-06-01 2007-05-23 Verifizierungsoperation für nichtflüchtige speicherung unter verwendung verschiedener spannungen

Country Status (6)

Country Link
EP (1) EP2022060B1 (de)
JP (1) JP4995273B2 (de)
KR (1) KR101012132B1 (de)
AT (1) ATE544157T1 (de)
TW (1) TWI333210B (de)
WO (1) WO2007143398A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101779247B (zh) * 2007-04-25 2013-01-30 桑迪士克科技股份有限公司 在非易失性存储器中的读取操作期间减小功耗
JP4510060B2 (ja) 2007-09-14 2010-07-21 株式会社東芝 不揮発性半導体記憶装置の読み出し/書き込み制御方法
JP2009193631A (ja) 2008-02-14 2009-08-27 Toshiba Corp 不揮発性半導体記憶装置
WO2011058934A1 (en) 2009-11-13 2011-05-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
JP5595901B2 (ja) * 2010-12-28 2014-09-24 株式会社東芝 不揮発性半導体記憶装置
JP2013069388A (ja) 2011-09-26 2013-04-18 Toshiba Corp 不揮発性半導体記憶装置
US8630118B2 (en) * 2011-11-09 2014-01-14 Sandisk Technologies Inc. Defective word line detection
US8861269B2 (en) 2013-03-05 2014-10-14 Sandisk Technologies Inc. Internal data load for non-volatile storage
KR102182804B1 (ko) 2014-07-29 2020-11-25 삼성전자주식회사 메모리 장치의 독출 방법
US11049578B1 (en) * 2020-02-19 2021-06-29 Sandisk Technologies Llc Non-volatile memory with program verify skip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3829088B2 (ja) * 2001-03-29 2006-10-04 株式会社東芝 半導体記憶装置
JP3938309B2 (ja) * 2002-01-22 2007-06-27 富士通株式会社 リードディスターブを緩和したフラッシュメモリ
JP3863485B2 (ja) * 2002-11-29 2006-12-27 株式会社東芝 不揮発性半導体記憶装置
JP3884448B2 (ja) * 2004-05-17 2007-02-21 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
KR20090007297A (ko) 2009-01-16
EP2022060B1 (de) 2012-02-01
WO2007143398A2 (en) 2007-12-13
EP2022060A2 (de) 2009-02-11
JP2009539203A (ja) 2009-11-12
TW200805371A (en) 2008-01-16
TWI333210B (en) 2010-11-11
WO2007143398A3 (en) 2008-03-13
JP4995273B2 (ja) 2012-08-08
KR101012132B1 (ko) 2011-02-07

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