ATE392713T1 - Verfahren zur herstellung von kondensator-über- bitleitung-speicherzellen - Google Patents

Verfahren zur herstellung von kondensator-über- bitleitung-speicherzellen

Info

Publication number
ATE392713T1
ATE392713T1 AT00948849T AT00948849T ATE392713T1 AT E392713 T1 ATE392713 T1 AT E392713T1 AT 00948849 T AT00948849 T AT 00948849T AT 00948849 T AT00948849 T AT 00948849T AT E392713 T1 ATE392713 T1 AT E392713T1
Authority
AT
Austria
Prior art keywords
bit line
over
storage cells
line storage
producing capacitor
Prior art date
Application number
AT00948849T
Other languages
English (en)
Inventor
John Zahurak
Kunal Parekh
Mark Fischer
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE392713T1 publication Critical patent/ATE392713T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Dram (AREA)
AT00948849T 1999-07-22 2000-07-19 Verfahren zur herstellung von kondensator-über- bitleitung-speicherzellen ATE392713T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/360,349 US6458649B1 (en) 1999-07-22 1999-07-22 Methods of forming capacitor-over-bit line memory cells

Publications (1)

Publication Number Publication Date
ATE392713T1 true ATE392713T1 (de) 2008-05-15

Family

ID=23417615

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00948849T ATE392713T1 (de) 1999-07-22 2000-07-19 Verfahren zur herstellung von kondensator-über- bitleitung-speicherzellen

Country Status (8)

Country Link
US (1) US6458649B1 (de)
EP (1) EP1196950B1 (de)
JP (2) JP2003505885A (de)
KR (1) KR100456358B1 (de)
AT (1) ATE392713T1 (de)
AU (1) AU6228600A (de)
DE (1) DE60038611T2 (de)
WO (1) WO2001008217A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6221711B1 (en) * 1998-05-11 2001-04-24 Micron Technology, Inc. Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry
US6589876B1 (en) * 1999-07-22 2003-07-08 Micron Technology, Inc. Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays
US6921692B2 (en) * 2003-07-07 2005-07-26 Micron Technology, Inc. Methods of forming memory circuitry
JP4528504B2 (ja) * 2003-08-22 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法
US20060019497A1 (en) * 2004-07-22 2006-01-26 Zhizhang Chen Reduced feature-size memory devices and methods for fabricating the same
US8022468B1 (en) * 2005-03-29 2011-09-20 Spansion Llc Ultraviolet radiation blocking interlayer dielectric
DE102005024944B3 (de) 2005-05-31 2006-12-28 Infineon Technologies Ag Kontaktstruktur für einen Stack-DRAM-Speicherkondensator
JP2010016249A (ja) * 2008-07-04 2010-01-21 Nec Electronics Corp 半導体装置の製造方法、及び半導体装置

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US5204286A (en) * 1991-10-15 1993-04-20 Micron Technology, Inc. Method of making self-aligned contacts and vertical interconnects to integrated circuits
US5296400A (en) 1991-12-14 1994-03-22 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a contact of a highly integrated semiconductor device
KR950000660B1 (ko) 1992-02-29 1995-01-27 현대전자산업 주식회사 고집적 소자용 미세콘택 형성방법
JP2522616B2 (ja) 1992-03-24 1996-08-07 株式会社東芝 半導体装置の製造方法
US5383088A (en) * 1993-08-09 1995-01-17 International Business Machines Corporation Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics
KR0137978B1 (ko) * 1994-10-12 1998-06-15 김주용 반도체 소자 제조방법
US5488011A (en) * 1994-11-08 1996-01-30 Micron Technology, Inc. Method of forming contact areas between vertical conductors
KR0140657B1 (ko) * 1994-12-31 1998-06-01 김주용 반도체 소자의 제조방법
JP3623834B2 (ja) 1995-01-31 2005-02-23 富士通株式会社 半導体記憶装置及びその製造方法
US5604147A (en) 1995-05-12 1997-02-18 Micron Technology, Inc. Method of forming a cylindrical container stacked capacitor
JPH0974174A (ja) 1995-09-01 1997-03-18 Texas Instr Japan Ltd 半導体装置及びその製造方法
KR0155886B1 (ko) * 1995-09-19 1998-10-15 김광호 고집적 dram 셀의 제조방법
JP3520144B2 (ja) * 1995-10-26 2004-04-19 株式会社ルネサステクノロジ 半導体記憶装置およびその製造方法
US5789289A (en) 1996-06-18 1998-08-04 Vanguard International Semiconductor Corporation Method for fabricating vertical fin capacitor structures
US5721154A (en) 1996-06-18 1998-02-24 Vanguard International Semiconductor Method for fabricating a four fin capacitor structure
US5670404A (en) 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
JP2800787B2 (ja) * 1996-06-27 1998-09-21 日本電気株式会社 半導体記憶装置の製造方法
JPH1079491A (ja) * 1996-07-10 1998-03-24 Fujitsu Ltd 半導体装置およびその製造方法
JP4064496B2 (ja) * 1996-07-12 2008-03-19 株式会社東芝 半導体装置及びその製造方法
US5706164A (en) * 1996-07-17 1998-01-06 Vangaurd International Semiconductor Corporation Method of fabricating high density integrated circuits, containing stacked capacitor DRAM devices, using elevated trench isolation and isolation spacers
JP3941133B2 (ja) * 1996-07-18 2007-07-04 富士通株式会社 半導体装置およびその製造方法
US5792687A (en) 1996-08-01 1998-08-11 Vanguard International Semiconductor Corporation Method for fabricating high density integrated circuits using oxide and polysilicon spacers
US5688713A (en) * 1996-08-26 1997-11-18 Vanguard International Semiconductor Corporation Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers
JPH10144886A (ja) * 1996-09-11 1998-05-29 Toshiba Corp 半導体装置及びその製造方法
JP3612913B2 (ja) * 1996-12-29 2005-01-26 ソニー株式会社 半導体装置の製造方法
JPH10200067A (ja) * 1996-12-29 1998-07-31 Sony Corp 半導体装置の製造方法
US5780338A (en) * 1997-04-11 1998-07-14 Vanguard International Semiconductor Corporation Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits
JPH10289986A (ja) 1997-04-15 1998-10-27 Fujitsu Ltd 半導体装置およびその製造方法
US5904521A (en) * 1997-08-28 1999-05-18 Vanguard International Semiconductor Corporation Method of forming a dynamic random access memory
US6060351A (en) 1997-12-24 2000-05-09 Micron Technology, Inc. Process for forming capacitor over bit line memory cell
JP3403052B2 (ja) * 1998-02-10 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US5837577A (en) 1998-04-24 1998-11-17 Vanguard International Semiconductor Corporation Method for making self-aligned node contacts to bit lines for capacitor-over-bit-line structures on dynamic random access memory (DRAM) devices

Also Published As

Publication number Publication date
US6458649B1 (en) 2002-10-01
KR20020037333A (ko) 2002-05-18
EP1196950A1 (de) 2002-04-17
DE60038611T2 (de) 2009-04-30
AU6228600A (en) 2001-02-13
EP1196950B1 (de) 2008-04-16
JP2003505885A (ja) 2003-02-12
WO2001008217A1 (en) 2001-02-01
JP2007134699A (ja) 2007-05-31
KR100456358B1 (ko) 2004-11-10
DE60038611D1 (de) 2008-05-29

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