ATE142803T1 - Deblockierverfahren eines multiprozessor-multibus-systems - Google Patents

Deblockierverfahren eines multiprozessor-multibus-systems

Info

Publication number
ATE142803T1
ATE142803T1 AT89123954T AT89123954T ATE142803T1 AT E142803 T1 ATE142803 T1 AT E142803T1 AT 89123954 T AT89123954 T AT 89123954T AT 89123954 T AT89123954 T AT 89123954T AT E142803 T1 ATE142803 T1 AT E142803T1
Authority
AT
Austria
Prior art keywords
bus
module
deblocking
function
freeing
Prior art date
Application number
AT89123954T
Other languages
English (en)
Inventor
Philippe Lallement
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Application granted granted Critical
Publication of ATE142803T1 publication Critical patent/ATE142803T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Small-Scale Networks (AREA)
  • Lock And Its Accessories (AREA)
AT89123954T 1988-12-30 1989-12-27 Deblockierverfahren eines multiprozessor-multibus-systems ATE142803T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8817506A FR2642246B1 (fr) 1988-12-30 1988-12-30 Procede de deblocage d'un systeme multiprocesseurs multibus

Publications (1)

Publication Number Publication Date
ATE142803T1 true ATE142803T1 (de) 1996-09-15

Family

ID=9373643

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89123954T ATE142803T1 (de) 1988-12-30 1989-12-27 Deblockierverfahren eines multiprozessor-multibus-systems

Country Status (12)

Country Link
US (1) US5553247A (de)
EP (1) EP0376249B1 (de)
JP (1) JP2724226B2 (de)
KR (1) KR0137020B1 (de)
CN (1) CN1020814C (de)
AT (1) ATE142803T1 (de)
AU (1) AU630647B2 (de)
CA (1) CA2006936C (de)
DE (1) DE68927157T2 (de)
ES (1) ES2091760T3 (de)
FR (1) FR2642246B1 (de)
MX (1) MX171836B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1048344C (zh) * 1994-05-24 2000-01-12 禹成海 一种适度耦合多处理机系统的体系结构
US6324622B1 (en) 1998-08-24 2001-11-27 International Business Machines Corporation 6XX bus with exclusive intervention
US6311255B1 (en) 1999-04-29 2001-10-30 International Business Machines Corporation System and method for selectively restricting access to memory for bus attached unit IDs
JP4140764B2 (ja) * 2001-03-19 2008-08-27 株式会社ルネサステクノロジ 半導体装置及びそのテスト方法
DE10136151C2 (de) * 2001-07-25 2003-06-05 Infineon Technologies Ag Multiprozessor-System mit zumindest zwei Mikroprozessoren mit optimaler Ausnutzung der zur Verfügung stehenden Ressourcen
US7130943B2 (en) * 2004-09-30 2006-10-31 Freescale Semiconductor, Inc. Data processing system with bus access retraction
US10470995B2 (en) 2018-02-21 2019-11-12 L'oreal Mascara compositions comprising a bimodal acrylic polymer and anionic, water-dispersible polyester and an aliphatic tackifier
CN109582626B (zh) * 2018-12-03 2021-10-29 郑州云海信息技术有限公司 一种访问总线的方法、装置、设备及可读存储介质
CN112948294B (zh) * 2021-03-19 2024-02-09 北京控制工程研究所 面向SOC的全域并行收发数据的双通道SpaceWire控制器及控制方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641505A (en) * 1969-06-25 1972-02-08 Bell Telephone Labor Inc Multiprocessor computer adapted for partitioning into a plurality of independently operating systems
JPS535098B2 (de) * 1972-11-22 1978-02-23
US4281380A (en) * 1978-12-27 1981-07-28 Harris Corporation Bus collision avoidance system for distributed network data processing communications system
US4488151A (en) * 1981-12-10 1984-12-11 Burroughs Corporation Arbiter switch for a concurrent network of processors
US4633392A (en) * 1982-04-05 1986-12-30 Texas Instruments Incorporated Self-configuring digital processor system with logical arbiter
US4527271A (en) * 1982-08-17 1985-07-02 The Foxboro Company Process control system with improved fault isolation
DE3246301A1 (de) * 1982-12-14 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erkennung von datenkollisionen in einem optischen datenbus
JPS59202753A (ja) * 1983-05-02 1984-11-16 Toshiba Corp デ−タ通信システム
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
JPS60183668A (ja) * 1984-03-01 1985-09-19 Canon Inc マルチプロセツサシステム
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
JPS619747A (ja) * 1984-06-26 1986-01-17 Matsushita Electric Ind Co Ltd バス制御装置
CA1247248A (en) * 1984-12-07 1988-12-20 Shouki Yoshida Transfer control equipment
JPS621051A (ja) * 1985-06-26 1987-01-07 Oki Electric Ind Co Ltd バス制御装置
US4751701A (en) * 1985-11-14 1988-06-14 Hughes Network Systems, Inc. TDM collision detector
US4858112A (en) * 1985-12-17 1989-08-15 General Electric Company Interface comprising message and protocol processors for interfacing digital data with a bus network
GB2187367B (en) * 1986-01-09 1990-03-28 Ricoh Kk Control system for local area network
US4719458A (en) * 1986-02-24 1988-01-12 Chrysler Motors Corporation Method of data arbitration and collision detection in a data bus
US4835737A (en) * 1986-07-21 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for controlled removal and insertion of circuit modules
DE3631086C2 (de) * 1986-09-12 1994-04-14 Telefonbau & Normalzeit Gmbh Schaltungsanordnung zur Fehlerbearbeitung in Mikroprozessorsystemen
US4707829A (en) * 1986-09-25 1987-11-17 Racal Data Communications Inc. CSMA-CD with channel capture
JPS63132365A (ja) * 1986-11-22 1988-06-04 Nec Corp バス調停制御方式
US4974153A (en) * 1987-09-04 1990-11-27 Digital Equipment Corporation Repeater interlock scheme for transactions between two buses including transaction and interlock buffers
CA1317667C (en) * 1987-11-02 1993-05-11 Michel Dufresne Catv subscriber terminal transmission control
US5140586A (en) * 1988-01-26 1992-08-18 E-Systems, Inc. Token associated data network communications protocol
US4977532A (en) * 1988-04-06 1990-12-11 Xycom, Inc. Industrial computer system with removable equipment drawer
US5129090A (en) * 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US4939510A (en) * 1988-08-22 1990-07-03 E-Systems, Inc. Broadband communications RF packet collision detection
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US4929940A (en) * 1988-11-18 1990-05-29 International Business Machines Corporation Collision crossbar switch
US5058101A (en) * 1988-12-15 1991-10-15 Bell Communications Research, Inc. Coherent detection loop distribution system
US5168568A (en) * 1989-02-06 1992-12-01 Compaq Computer Corporation Delaying arbitration of bus access in digital computers
CA2018301A1 (en) * 1990-06-05 1991-12-05 David P. G. Schenkel Packet communication system and method of clearing communication bus

Also Published As

Publication number Publication date
FR2642246A1 (fr) 1990-07-27
DE68927157D1 (de) 1996-10-17
KR0137020B1 (ko) 1998-06-15
AU630647B2 (en) 1992-11-05
EP0376249B1 (de) 1996-09-11
FR2642246B1 (fr) 1991-04-05
EP0376249A1 (de) 1990-07-04
MX171836B (es) 1993-11-18
CA2006936A1 (fr) 1990-06-30
JPH02226356A (ja) 1990-09-07
CN1020814C (zh) 1993-05-19
US5553247A (en) 1996-09-03
JP2724226B2 (ja) 1998-03-09
KR900010537A (ko) 1990-07-07
ES2091760T3 (es) 1996-11-16
CA2006936C (fr) 1999-10-19
DE68927157T2 (de) 1997-02-06
CN1044196A (zh) 1990-07-25
AU4735989A (en) 1990-07-05

Similar Documents

Publication Publication Date Title
DK189889A (da) Multibusdatamatanlaeg med busudpegningsanlaeg
KR960035261A (ko) 적응성 인터럽트 맵핑 메카니즘 및 방법을 사용하는 다중처리 시스템
EP0111840A3 (de) Zugriffsteuerungsverfahren für Multiprozessorsysteme
EP0485690A3 (en) Parallel associative processor system
EP0223413A3 (en) Interrupt handling in a multiprocessor computing system
HK1019250A1 (en) Microprocessor architecture capable of supporting multiple heterogenous processors
EP0635792A3 (de) Verfahren zur Koordination von parallelen Zugriffen mehrerer Prozessoren auf Resourcenkonfigurationen.
GB2298503A (en) Multiple programmable interrupt controllers in a multi-processor system
EP0566515A3 (en) System clustering via serially attached remote i/o busses
ATE142803T1 (de) Deblockierverfahren eines multiprozessor-multibus-systems
ES2004366A6 (es) Unidad de arbitraje y metodo para arbitrar acceso a una linea general de datos y sistema de proceso de datos correspondiente.
ATE80480T1 (de) Vorrichtung und verfahren zur zugriffsteuerung in einer mehrcachespeicherdatenverarbeitungsanordnung.
MY116719A (en) Using intelligent bridges with pico-code to improve interrupt response
JPS5741727A (en) Interruption controlling sysyem
CA2145553A1 (en) Multi-Processor System Including Priority Arbitrator for Arbitrating Request Issued from Processors
TW369632B (en) Computer system
ATE51310T1 (de) Datenverarbeitungssystem mit modulen, die zahlenfolgen auf steuerleitungen auf eine logische ''oder''-weise kombinieren zur benutzung eines gemeinsam genutzten busses.
KR930004910Y1 (ko) 다중처리기 시스템에서의 데이터버스 중재기
KR960029993A (ko) 컴퓨터 분야의 인터럽트 제어 장치
JPS6459558A (en) Data processing system
SU1084795A1 (ru) Устройство прерывани
JPS5518720A (en) Multiple computer system
JPS5733473A (en) Memory access control system
JPS56155453A (en) Program execution controlling system
Mamatov et al. Efficiency of multiprocessor computers with multiple-module storage.

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee