ES2004366A6 - Unidad de arbitraje y metodo para arbitrar acceso a una linea general de datos y sistema de proceso de datos correspondiente. - Google Patents

Unidad de arbitraje y metodo para arbitrar acceso a una linea general de datos y sistema de proceso de datos correspondiente.

Info

Publication number
ES2004366A6
ES2004366A6 ES8700202A ES8700202A ES2004366A6 ES 2004366 A6 ES2004366 A6 ES 2004366A6 ES 8700202 A ES8700202 A ES 8700202A ES 8700202 A ES8700202 A ES 8700202A ES 2004366 A6 ES2004366 A6 ES 2004366A6
Authority
ES
Spain
Prior art keywords
unit
access
arbitration
data processing
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8700202A
Other languages
English (en)
Inventor
Robert E Stewart
Paul J Natusch
Eugene L Yu
James B Keller
John F Henry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of ES2004366A6 publication Critical patent/ES2004366A6/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

UNIDAD DE ARBITRAJE Y METODO PARA ARBITRAR ACCESO A UNA LINEA GENERAL DE DATOS, Y SISTEMA DE PROCESO DE DATOS CORRESPONDIENTE, EN DONDE UNA UNIDAD DE ARBITRAJE (20) CONCEDE DE UNA UNIDAD (10, 11, 13-15) A UNA LINEA GENERAL (19). CUANDO UNA UNIDAD SOLICITANTE NO PUEDE ACCEDER A UNA UNIDAD OBJETIVO, ESTA PROPORCIONA INMEDIATAMENTE UNA SEÑAL DE OCUPADO A TODAS LAS UNIDADES, INCLUIDA LA UNIDAD (20). CUALQUIER UNIDAD QUE HAYA SOLICITADO ACCESO A LA LINEA GENERAL DEL SISTEMA ANTES DE GENERARSE LA SEÑAL DE OCUPADO VOLVERA A SOLICITAR ACCESO A DICHA LINEA DESPUES DE QUE SE INTRODUZCA DICHA SEÑAL. ESTA SEÑAL INHIBE A LA UNIDAD DE ARBITRAJE (20) HASTA QUE LA UNIDAD QUE RECIBIO LA SEÑAL DE OCUPADO PUEDA REAFIRMAR SU PETICION DE ACCESO A LA LINEA GENERAL. EL INVENTO ES ESPECIALMENTE UTIL PARA INTERCAMBIAR SEÑALES LOGICAS ENTRE SUBSISTEMAS DE PROCESO DE DATOS.
ES8700202A 1986-01-29 1987-01-28 Unidad de arbitraje y metodo para arbitrar acceso a una linea general de datos y sistema de proceso de datos correspondiente. Expired ES2004366A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/823,775 US4858173A (en) 1986-01-29 1986-01-29 Apparatus and method for responding to an aborted signal exchange between subsystems in a data processing system

Publications (1)

Publication Number Publication Date
ES2004366A6 true ES2004366A6 (es) 1989-01-01

Family

ID=25239676

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8700202A Expired ES2004366A6 (es) 1986-01-29 1987-01-28 Unidad de arbitraje y metodo para arbitrar acceso a una linea general de datos y sistema de proceso de datos correspondiente.

Country Status (11)

Country Link
US (1) US4858173A (es)
EP (1) EP0292499A1 (es)
JP (1) JPH01501425A (es)
KR (1) KR910007030B1 (es)
CN (1) CN1012224B (es)
AU (1) AU7026387A (es)
CA (1) CA1275328C (es)
ES (1) ES2004366A6 (es)
IL (1) IL81424A (es)
IN (1) IN170450B (es)
WO (1) WO1987004828A1 (es)

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JP2633900B2 (ja) * 1988-04-22 1997-07-23 株式会社日立製作所 共通バス制御方法
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US4953081A (en) * 1988-12-21 1990-08-28 International Business Machines Corporation Least recently used arbiter with programmable high priority mode and performance monitor
US5155854A (en) * 1989-02-03 1992-10-13 Digital Equipment Corporation System for arbitrating communication requests using multi-pass control unit based on availability of system resources
DE3917715A1 (de) * 1989-05-31 1990-12-06 Teldix Gmbh Rechnersystem
US5265212A (en) * 1992-04-01 1993-11-23 Digital Equipment Corporation Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types
US5553248A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
US5535395A (en) * 1992-10-02 1996-07-09 Compaq Computer Corporation Prioritization of microprocessors in multiprocessor computer systems
US5533204A (en) * 1994-04-18 1996-07-02 Compaq Computer Corporation Split transaction protocol for the peripheral component interconnect bus
US6073199A (en) * 1997-10-06 2000-06-06 Cisco Technology, Inc. History-based bus arbitration with hidden re-arbitration during wait cycles
GB2337138B (en) * 1998-01-30 2002-12-18 * Sgs-Thomson Microelectronics Limited Arbitration
GB2341771B (en) * 1998-09-18 2003-10-22 Pixelfusion Ltd Address decoding and access control for bus modules
US6614437B1 (en) * 1999-01-25 2003-09-02 Sony Corporation Apparatus and method for efficient memory utilization in an electronic system
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
US8923307B2 (en) * 2003-07-14 2014-12-30 Broadcom Corporation Method and system for an integrated dual port gigabit ethernet controller chip
KR101519825B1 (ko) * 2008-12-05 2015-05-13 삼성전자주식회사 데이터 처리 장치 및 그 제어 방법
CN102880143B (zh) * 2012-09-27 2014-10-22 中国船舶重工集团公司第七一九研究所 单can控制器热冗余can总线系统及其实现方法

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US3676860A (en) * 1970-12-28 1972-07-11 Ibm Interactive tie-breaking system
US4016539A (en) * 1973-09-12 1977-04-05 Nippon Electric Company, Ltd. Asynchronous arbiter
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JPS512133A (ja) * 1974-06-22 1976-01-09 Kyoshi Sawa Oritatamitorankushunogatajitensha
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US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
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Also Published As

Publication number Publication date
EP0292499A1 (en) 1988-11-30
AU7026387A (en) 1987-08-25
JPH01501425A (ja) 1989-05-18
IL81424A0 (en) 1987-08-31
KR880700901A (ko) 1988-04-13
CN87102175A (zh) 1987-12-09
WO1987004828A1 (en) 1987-08-13
IN170450B (es) 1992-03-28
KR910007030B1 (ko) 1991-09-16
IL81424A (en) 1991-01-31
US4858173A (en) 1989-08-15
CA1275328C (en) 1990-10-16
CN1012224B (zh) 1991-03-27

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980401