EP0376249B1 - Deblockierverfahren eines Multiprozessor-Multibus-Systems - Google Patents

Deblockierverfahren eines Multiprozessor-Multibus-Systems Download PDF

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Publication number
EP0376249B1
EP0376249B1 EP89123954A EP89123954A EP0376249B1 EP 0376249 B1 EP0376249 B1 EP 0376249B1 EP 89123954 A EP89123954 A EP 89123954A EP 89123954 A EP89123954 A EP 89123954A EP 0376249 B1 EP0376249 B1 EP 0376249B1
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Prior art keywords
bus
signal
module
decongestion
board
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Expired - Lifetime
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EP89123954A
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English (en)
French (fr)
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EP0376249A1 (de
Inventor
Philippe Lallement
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Alcatel CIT SA
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Alcatel CIT SA
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • the field of the invention is that of multiprocessor systems of the type comprising at least one processing module consisting of processors connected to a main bus. More generally, the invention relates to multibus systems, in which several processing modules communicate with each other through bus couplers.
  • each processor includes means for managing access to the main bus of the module to which it belongs, according to a two-phase process.
  • a first phase corresponding for example to a clock cycle
  • all the requests for access to the bus originating from all the processors of the module are processed by a priority arbitration logic, so as to identify a winner of the allocation process. This winner then becomes the "next master" of the bus.
  • a second phase that is to say as soon as the module bus is released, the bus socket circuit associated with the winning processor ensures exclusive access for the processor to the bus by transmitting a signal bus mastery.
  • the bus couplers ensuring communication between the different processing modules on different buses cooperate in pairs from one bus to another, to establish bidirectional links with conventional access request on the bus corresponding recipient.
  • the disturbance of the signals passing by the bus can cause a blocking either of the allocators or of the bus socket and bus management logic of the cards present on the bus.
  • the blockage occurs at a time when a bus coupler is in communication mode with a remote module, the blockage can propagate to other buses; in the worst case, a complete blocking of the entire configuration can occur.
  • the reset signal consists in acting on the connection registers of the processors of each module, and of the bus couplers, so as to prohibit each card from transmitting on the bus, without inhibiting its capacity to receive the signals passing through the bus. .
  • the system board may experience in certain circumstances difficulties in taking the bus control, either due to a conflict with a bus coupler card, or following the loss of access priority on the bus.
  • the invention aims to overcome these drawbacks by providing a bus unblocking system by means of a perfectly controlled process allowing progressive and iterative unblocking of a multibus system undergoing general blocking.
  • the method of the invention thus has the advantage of making it possible to isolate the faulty module from the other modules of the system, without disturbing the software configuration of the system, or any bus cycles in progress.
  • the solution of the invention has perfect compatibility with existing systems for managing conflicts of simultaneous reciprocal access requests between two buses.
  • the method of the invention as defined in the claims is finally also usable to allow the emission of several consecutive cycles without releasing the bus.
  • the method of the invention is applicable in multiprocessor systems in which said signal arbitration result of the allocator is provided by an arbitration logic of the module, said arbitration logic receiving as input a participation signal in the allocation of each of the processors transmitting a request for access to the bus during the same cycle.
  • said single decongestion signal inhibits said participation in the allocation of each of said processors of the module.
  • the unblocking method is characterized in that said single decongestion signal is sent to the allocator and the bus socket circuit of each of said connected couplers to the bus to unlock.
  • the invention advantageously provides that said unblocking card iteratively decongests it from each of the buses starting from the most close, by the alternation of an operation of transmitting the decongestion signal on the bus of the unlocking card to release it, then of an operation of sending to the bus coupler of said bus freed from a transmission order the decongestion signal to the next bus and / or an inhibit order from the allocator of said coupler to isolate said next bus when it fails.
  • said bus decongestion signal and the collision resolution signal consist of a single signal.
  • said decongestion card comprises firstly means for identifying the faulty card and / or the module of the faulty card causing the blockage, and secondly means for neutralizing said card , and / or isolation of said module.
  • said decongestion card is advantageously the system reset card of said multiprocessor system and / or a supervision card of one of the processing modules of said multiprocessor system.
  • the multiprocessor multibus system represented in FIG. 1 diagrams an application in the form of a data switch.
  • a data switch has the function of receiving digital data supplied by transmission lines 10, and of sorting and grouping this data in multiprocessor processing means, so as to redirect them over suitable transmission lines 10.
  • Each of these buses 11, 12, 13, corresponds to a processing module each comprising several processors 14, possibly each associated with a local memory 15 through a local bus 16.
  • the switching bus 13 also comprises a terminal bus coupler 17 which, associated with a processor 18, manages the terminal transmission bus 19 for connection of the transmission / reception lines 10.
  • the management bus 11 also includes a system card 20, the role of which is to monitor the entire multiprocessor multibus system.
  • Each bus receives, for example, a maximum number of sixteen processors (master card), the other locations possibly corresponding to physical addresses of slave cards (for example memories).
  • the buses 11, 12, 13, of the various modules of the multiprocessor system communicate through bus couplers 21 connected in pairs.
  • FIG. 2 illustrates the structure and the operation of a pair of bus couplers 22, 23, ensuring communication between two buses 24, 25.
  • bus couplers are possible. By way of example, mention will be made for the memory of the couplers having an operation of the "letterbox" type.
  • Each coupler 22, 23 comprises on the one hand a module 26 2 26 3 for receiving data from the buses 24, 25, respectively, and on the other hand a module 272, 273 for transmitting on the bus 24, 25, data received from the remote coupler 23,22, respectively. Consequently, the connection of the two couplers 22, 23 takes place on the one hand between the receiver module 26 2 and the transmitter module 27 3 (data transfer from bus 24 to bus 25), and on the other hand between the receiver module 26 3 and transmitter module 27 2 (data transfer from bus 25 to bus 24).
  • Each of the transmitter modules 26 2 , 26 3 cooperates with a memory 28 2 , 28 3 comprising specific address tables of the remote buses.
  • the transfer decisions taken by each coupler 22, 23 depend on the content of these address tables.
  • each transmitter module 27 2 , 27 3 cooperates with means 29 2 , 29 3 , for managing access to the bus 24, 25.
  • FIG. 3 represents the logic for requesting access to the bus of each master processor of the single bus processing modules 11, 12, 13.
  • the logic for requesting access comprises on the one hand a system for allocating access 31, synchronous and distributed, operating according to a process of arbitration of the access requests 30 expressed by the processors, and on the other hand a bus socket logic 32, connected to the allocation system 31 by a signal 33 d 'authorization or non-authorization to take a bus depending on the result of the allocated allocation operation.
  • the allocation system 31 consists on the one hand of a bus request logic 34, formed of a rocker of synchronization with the allocator clock, and on the other hand of an allocator circuit 35 proper, receiving the access requests 47 from the logic 34, and responsible for the arbitration of the access requests, and for the transmission of the arbitration result 33 for the associated processor.
  • Arbitration is either fixed priority or rotating priority.
  • the 16 physical addresses of the master card connected to bus 12 are divided into 2 groups of 8 addresses, one of which has priority (signal GP /). In each group, priority is assigned via priority signals PR1 to PR7.
  • the signals GP / and PR1 and PR7 are input / output in open collector on the main bus 12.
  • the priorities are increasing in the order of 0 to 7, and each assigned to a processor connected to a physical address of the bus.
  • the definition of the next master of bus 12 is performed by a logic for overwriting the "1" on the PR signals: at the end of an allocation cycle, the winner of the arbitration is the one who belongs to the active GP group and who has his active PR thread.
  • the priority locations (PR0 to PR7) are variable, reassigning the lowest priority to each last card that took the bus.
  • the allocator circuit 35 also includes other wires for communication with the bus 12, in particular wires for identifying the address of the physical location of the wires for the number of the current master of the bus (use with rotating priority), a allocator synchronization clock wire 35, and a "bus busy" wire.
  • a participating processor When a participating processor is elected, following the allocation operation, it transmits this information to the bus socket logic 32 by the allocation result signal 33.
  • This logic 32 monitors the bus 12, and at at the end of the current cycle, takes control of the bus and sends a signal 36 to the allocator 35 authorizing a new allocation for the next bus master.
  • the bus socket circuit 32 transmits on the bus 12 the signal of the existence of an address during the cycle (strobe address) or of the existence of data during the cycle (data strobe), and receives the data acknowledgment signals. Finally, circuit 32 also sends signals 37, 38 for controlling the address bus and the data bus.
  • the card also includes a wire 39 for disabling the allocator 35, on command of reset commands 40, or on an external inhibition order 41, for example a disconnection order transmitted by the system card 20
  • the bus 34 and bus socket 32 request logic also include reset wires 42, 43 respectively.
  • the transfer cycles are asynchronous, so that the bus is blocked by the requester "master card” until the response from the addressed card. If the recipient does not respond, a "watchdog” is triggered on the "requesting" card, which releases the bus, and leaves for error processing.
  • the bus couplers 21 analyze the addresses which pass on their bus, and after address filtering, open the way to the remote bus when necessary.
  • the processor 14 connected to the bus 11 can address the processor 14 or the memory 15 connected to the bus 12.
  • the operation first blocks the bus 11.
  • the coupler 21 of the bus 11 recognizes the requested address , and opens the way to the bus 12 which it takes and blocks when the latter is free.
  • the recipient responds, and the sending processor then frees the two buses 11 and 12 on receipt of the recipient response.
  • a transfer from bus 11 to bus 13 will require the use of intermediate bus 12, in the absence of a specific pair of couplers putting buses 11 and 13 in direct communication.
  • the watchdogs of each of the processors are calculated from so as to allow the execution of a transfer involving the cascade of the maximum number of buses concerned by the most distant transfer.
  • the disturbance of the bus signals leads to blockage of the allocators 35 or of the bus socket logic 32 of the cards connected to the bus.
  • the blocking occurs at a time when the code present on the address bus corresponds to the address of a card located on another bus, the blocking can spread to the other buses via the coupler cards of bus 21.
  • permanent zeroing of the following signals can cause a propagatable disturbance on several adjacent buses.
  • the bus decongestion function constitutive of the present invention, consists in the emission of a single specific decongestion signal 45, represented in bold line in FIG. 3.
  • the FINHAL signal 46 from the inhibition module 44 is generated in synchronism with the clock, and is maintained throughout the duration of the single decongestion signal 45. It passes through the same wire as the signal 39 for inhibiting the allocator 35 on external order 40, 41.
  • the decongestion signal causes the reset of the flip-flop internal to the bus socket logic 32 which generates the signals 38 for controlling the address and data buses.
  • the procedure used then allows a restart of the requests canceled by action on the bus request logic 34.
  • decongestion signal 45, 46 as a "superpriority" signal at the level of allocators 35.
  • the decongestion process thus does not disturb either the software configuration or any bus cycles in progress.
  • FIG. 4 illustrates the unblocking method implemented in the case of a blockage involving several buses.
  • the master card 84 connected to the bus 81 is at the origin of a blockage in a cycle bound for the slave card 85 connected to bus 83.
  • the three buses 81, 82, 83 are therefore blocked.
  • the blocking was for example caused by a situation in which the signal for the existence of an address during the ASG / cycle is forced to zero on the bus 81; it propagates on the buses 82 and 83 in the direction of propagation 87 due to the fact that the bus couplers 86 12 and 86 23 ensure communication due to the fact of a filtering address filtering situation.
  • the master card 88 or the system card (not shown) detects the blocking of the configuration, and will therefore give itself the means to isolate the faulty bus by putting the allocators of the bus coupler cards in inhibition state 86 32 , 86 23 , 86 21 , and 86 12 giving access to the faulty bus 81.
  • the installation of the decongestion means by single signal is advantageously carried out in multibus systems with bus couplers equipped with means for managing requests for simultaneous reciprocal access (“collision” management), as described below. Indeed, in this case, there is a entirely favorable synergy between collision management and decongestion, from the point of view of the similarity both of the structural and functional characteristics of the corresponding systems.
  • the "collision" situation can be presented in relation to FIG. 4.
  • the card 84 wants to reach the card 91, it takes and blocks the bus 81. If at this time, the card 90 wants, for its part, to reach the card 89, it takes and blocks the bus 82. The two buses 81 and 82 being blocked, couplers 86 12 and 86 21 cannot respond: there is a collision. If no specific unlocking device is provided, the system remains in the blocked state until the appearance of "watchdogs" on the master cards 84 and 90 which go into error processing.
  • FIG. 5 diagrams the functional modules to be provided in the system board for managing the emission of the single decongestion and collision resolution signal.
  • a bistable circuit making it possible to transmit the single decongestion signal.
  • This bistable is addressable by program in the private area of system boards and UTS, and in the area of coupling of bus couplers.
  • This decongestion / collision bistable is for example set to 1 by a write cycle, then set to zero by another write cycle.
  • the decongestion signal sent is active on all cards on the bus, except on the issuing card.
  • FIG. 6 schematizes the assembly in the case of a pair of bus couplers 61, 62 ensuring communication between a first bus 63 and a second bus 64.
  • the mechanism is shown in one direction, but obviously operates symmetrically in the other direction.
  • the collision / decongestion bistable 65 in the coupler 61 transmits the decongestion / collision 66 signal by the associated bus coupler 62 and therefore on the remote bus 64.
  • Figures 5 and 7 show schematically the logic modules to be provided in the system board on the one hand, and in the bus couplers on the other hand respectively, for the management of the single collision / decongestion signal.
  • an internal signal 51 for controlling the transmission of the congestion / decongestion signal is provided by a software order 52 through a flip-flop 53.
  • the single congestion / decongestion signal 55 is sent on the bus through a buffer circuit 54.
  • a buffer 56 takes them into account when receiving the bus.
  • the internal collision signal 71 is generated by an external software order 72 through a flip-flop 73.
  • the software order comes from the remote bus coupler (flip-flop 65 of the coupler 61 of FIG. 6).
  • the internal collision signal 71 generates the transmission of the collision / decongestion signal 75 on its bus through a buffer 74.
  • the bus coupler will also transmit the collision / decongestion signal 75 on detection of a double reciprocal simultaneous request 70, when the bus coupler card has no priority. This situation corresponds to the detection of an actual collision on the bus pair, during which the bus coupler does not have priority inhibits the caller on his bus.
  • the last signal 93 (taking into account the collision on the remote bus) is necessary to release the allocator of the priority bus coupler which has been activated by the requester of the non-priority bus (requester which has been inhibited, as already mentioned , via the non-priority bus coupler).

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Time-Division Multiplex Systems (AREA)
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Claims (7)

  1. Verfahren zur Entblockierung eines Multiprozessorsystems, das mindestens einen Verarbeitungsmodul enthält, der von an einen einzigen Hauptbus angeschlossenen Prozessoren gebildet wird, wobei jeder Prozessor eine Zelle zur Verwaltung des Zugangs zum Hauptbus in zwei Phasen besitzt, die einerseits ein Buszuweisungssystem, das im Verlauf einer ersten Phase ein Signal bezüglich des positiven oder negativen Ergebnisses der Streitschlichtung der während eines bestimmten Zyklus von den Prozessoren des Moduls ausgesprochenen Zugangsanfragen liefert, und die andererseits eine Schaltung zur Übernahme der Busleitung enthält, die in einer zweiten Phase den Zugang zum Bus des Prozessors durch Aussenden eines Signals gewährleistet, das die Übernahme der Busleitung im Fall eines positiven Ergebnisses im Zuweisungssystem während der ersten Phase bedeutet, dadurch gekennzeichnet, daß das Verfahren darin besteht, einer spezifischen Entblockierkarte (20, 88) eine Funktion der Erfassung der Blockierung des Moduls und eine Funktion der Freigabe der Busleitung (82) des Moduls (82, 90, 91) zu übertragen, und daß die Funktion der Freigabe der Busleitung darin besteht, ein einziges Signal (45, 55, 75) zur Entblockierung auszusenden, das für alle Prozessoren (90, 8623, 8621) des Moduls einerseits das Ergebnis der Zuweisung (33) negativ macht und andererseits das Signal (37, 38), mit dem der Bus übernommen wurde, annuliert.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das vom Zuweisungssystem (31) kommende Signal (33) mit dem Ergebnis der Zugangszuweisung von einer Streitschlichtungsschaltung (35) des Moduls geliefert wird, wobei die Streitschlichtungsschaltung (35) eingangsseitig ein Zugangsanfragesignal (47) von jedem der Prozessoren empfängt, die eine Zugangsanfrage an den Bus (12) während eines gegebenen Zyklus richten, wobei das einzige Entblockierungssignal (45, 55, 75) die Teilnahme (47) an der Zuweisung jedes der Prozessoren des Moduls sperrt.
  3. Verfahren nach einem beliebigen der Ansprüche 1 oder 2 für den Fall eines Mehrfachbussystems mit mindestens zwei Verarbeitungsmoduln, die je mit mindestens einem anderen Modul über ein symmetrisches Paar von Hauptbuskopplern (21, 22, 23) verkehren, wobei jeder Buskoppler an den Zuweisungsund Busübernahmemechanismen zum Zielbus teilhat, dadurch gekennzeichnet, daß das einzige Entblockierungssignal (45, 55, 75) zur Zuweisungsschaltung und zur Busübernahmeschaltung jedes der an den Bus angeschlossenen Koppler (21, 22, 23) gesendet wird.
  4. Verfahren nach Anspruch 3 für den Fall einer Blockierung mehrerer miteinander über Hauptbuskoppler (21, 22, 23) verbundener Busleitungen (81, 82, 83) in Kaskade, dadurch gekennzeichnet, daß die Entblockierungskarte (20, 88) jede der Busleitungen (82, 83) ausgehend vom nächstliegenden Bus (83) iterativ entblockiert, indem abwechselnd das Entblokkiersignal (45, 55, 75) auf jeden Bus zu dessen Freigabe gesendet wird und dann ein Befehl zur Übermittlung des Entblockiersignals an den nächstfolgenden Bus (82) dem Buskoppler (8632) der freigegebenen Busleitung (83) und/oder ein Befehl zur Sperrung des Zuweisungssystems des Kopplers zugeleitet wird, um den nächstfolgenden Bus zu isolieren, wenn er gestört ist.
  5. Verfahren nach einem beliebigen der Ansprüche 3 und 4 für ein Multiprozessorsystem, wie es im Anspruch 1 vorgesehen ist, wobei die Buskoppler mit Mitteln zur Abwicklung der Kollisionen zwischen reziproken Zugangsanfragen während eines gleichen Zyklus zwischen zwei benachbarten Busleitungen versehen sind, dadurch gekennzeichnet, daß das Busentblockiersignal und das Signal zur Behebung von Kollisionen von einem einzigen Signal gebildet werden.
  6. Verfahren nach einem beliebigen der Ansprüche 1 und 5, in dem die Entblockierkarte einerseits Mittel zur Identifizierung der gestörten Karte und/oder des Moduls der gestörten Karte, auf der die Blockierung beruht, und andererseits Mittel zur Neutralisierung der Karte und/oder zur Isolierung des Moduls enthält.
  7. Verfahren nach Anspruch 6, in dem die Entblockierkarte die Systemkarte (20) zur Rücksetzung des Multiprozessorsystems und/oder eine Überwachungskarte (88) eines der Verarbeitungsmoduln des Multiprozessorsystems ist.
EP89123954A 1988-12-30 1989-12-27 Deblockierverfahren eines Multiprozessor-Multibus-Systems Expired - Lifetime EP0376249B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8817506 1988-12-30
FR8817506A FR2642246B1 (fr) 1988-12-30 1988-12-30 Procede de deblocage d'un systeme multiprocesseurs multibus

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EP0376249A1 EP0376249A1 (de) 1990-07-04
EP0376249B1 true EP0376249B1 (de) 1996-09-11

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US (1) US5553247A (de)
EP (1) EP0376249B1 (de)
JP (1) JP2724226B2 (de)
KR (1) KR0137020B1 (de)
CN (1) CN1020814C (de)
AT (1) ATE142803T1 (de)
AU (1) AU630647B2 (de)
CA (1) CA2006936C (de)
DE (1) DE68927157T2 (de)
ES (1) ES2091760T3 (de)
FR (1) FR2642246B1 (de)
MX (1) MX171836B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1048344C (zh) * 1994-05-24 2000-01-12 禹成海 一种适度耦合多处理机系统的体系结构
US6324622B1 (en) 1998-08-24 2001-11-27 International Business Machines Corporation 6XX bus with exclusive intervention
US6311255B1 (en) 1999-04-29 2001-10-30 International Business Machines Corporation System and method for selectively restricting access to memory for bus attached unit IDs
KR100886928B1 (ko) * 2001-03-19 2009-03-09 가부시키가이샤 히타치세이사쿠쇼 반도체장치 및 그 테스트방법
DE10136151C2 (de) * 2001-07-25 2003-06-05 Infineon Technologies Ag Multiprozessor-System mit zumindest zwei Mikroprozessoren mit optimaler Ausnutzung der zur Verfügung stehenden Ressourcen
US7130943B2 (en) * 2004-09-30 2006-10-31 Freescale Semiconductor, Inc. Data processing system with bus access retraction
US10470995B2 (en) 2018-02-21 2019-11-12 L'oreal Mascara compositions comprising a bimodal acrylic polymer and anionic, water-dispersible polyester and an aliphatic tackifier
CN109582626B (zh) * 2018-12-03 2021-10-29 郑州云海信息技术有限公司 一种访问总线的方法、装置、设备及可读存储介质
CN112948294B (zh) * 2021-03-19 2024-02-09 北京控制工程研究所 面向SOC的全域并行收发数据的双通道SpaceWire控制器及控制方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641505A (en) * 1969-06-25 1972-02-08 Bell Telephone Labor Inc Multiprocessor computer adapted for partitioning into a plurality of independently operating systems
JPS535098B2 (de) * 1972-11-22 1978-02-23
US4281380A (en) * 1978-12-27 1981-07-28 Harris Corporation Bus collision avoidance system for distributed network data processing communications system
US4488151A (en) * 1981-12-10 1984-12-11 Burroughs Corporation Arbiter switch for a concurrent network of processors
US4633392A (en) * 1982-04-05 1986-12-30 Texas Instruments Incorporated Self-configuring digital processor system with logical arbiter
US4527271A (en) * 1982-08-17 1985-07-02 The Foxboro Company Process control system with improved fault isolation
DE3246301A1 (de) * 1982-12-14 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erkennung von datenkollisionen in einem optischen datenbus
JPS59202753A (ja) * 1983-05-02 1984-11-16 Toshiba Corp デ−タ通信システム
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
JPS60183668A (ja) * 1984-03-01 1985-09-19 Canon Inc マルチプロセツサシステム
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
JPS619747A (ja) * 1984-06-26 1986-01-17 Matsushita Electric Ind Co Ltd バス制御装置
JPH07104826B2 (ja) * 1984-12-07 1995-11-13 日本電気株式会社 転送制御装置
JPS621051A (ja) * 1985-06-26 1987-01-07 Oki Electric Ind Co Ltd バス制御装置
US4751701A (en) * 1985-11-14 1988-06-14 Hughes Network Systems, Inc. TDM collision detector
US4858112A (en) * 1985-12-17 1989-08-15 General Electric Company Interface comprising message and protocol processors for interfacing digital data with a bus network
GB2187367B (en) * 1986-01-09 1990-03-28 Ricoh Kk Control system for local area network
US4719458A (en) * 1986-02-24 1988-01-12 Chrysler Motors Corporation Method of data arbitration and collision detection in a data bus
US4835737A (en) * 1986-07-21 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for controlled removal and insertion of circuit modules
DE3631086C2 (de) * 1986-09-12 1994-04-14 Telefonbau & Normalzeit Gmbh Schaltungsanordnung zur Fehlerbearbeitung in Mikroprozessorsystemen
US4707829A (en) * 1986-09-25 1987-11-17 Racal Data Communications Inc. CSMA-CD with channel capture
JPS63132365A (ja) * 1986-11-22 1988-06-04 Nec Corp バス調停制御方式
US4974153A (en) * 1987-09-04 1990-11-27 Digital Equipment Corporation Repeater interlock scheme for transactions between two buses including transaction and interlock buffers
CA1317667C (en) * 1987-11-02 1993-05-11 Michel Dufresne Catv subscriber terminal transmission control
US5140586A (en) * 1988-01-26 1992-08-18 E-Systems, Inc. Token associated data network communications protocol
US4977532A (en) * 1988-04-06 1990-12-11 Xycom, Inc. Industrial computer system with removable equipment drawer
US5129090A (en) * 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US4939510A (en) * 1988-08-22 1990-07-03 E-Systems, Inc. Broadband communications RF packet collision detection
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US4929940A (en) * 1988-11-18 1990-05-29 International Business Machines Corporation Collision crossbar switch
US5058101A (en) * 1988-12-15 1991-10-15 Bell Communications Research, Inc. Coherent detection loop distribution system
US5168568A (en) * 1989-02-06 1992-12-01 Compaq Computer Corporation Delaying arbitration of bus access in digital computers
CA2018301A1 (en) * 1990-06-05 1991-12-05 David P. G. Schenkel Packet communication system and method of clearing communication bus

Also Published As

Publication number Publication date
CA2006936A1 (fr) 1990-06-30
MX171836B (es) 1993-11-18
ES2091760T3 (es) 1996-11-16
JPH02226356A (ja) 1990-09-07
CA2006936C (fr) 1999-10-19
DE68927157D1 (de) 1996-10-17
EP0376249A1 (de) 1990-07-04
AU630647B2 (en) 1992-11-05
JP2724226B2 (ja) 1998-03-09
US5553247A (en) 1996-09-03
ATE142803T1 (de) 1996-09-15
FR2642246A1 (fr) 1990-07-27
KR900010537A (ko) 1990-07-07
KR0137020B1 (ko) 1998-06-15
CN1020814C (zh) 1993-05-19
CN1044196A (zh) 1990-07-25
DE68927157T2 (de) 1997-02-06
FR2642246B1 (fr) 1991-04-05
AU4735989A (en) 1990-07-05

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