MX171836B - Proceso de desbloque en un sistema multiprocesador de ductos multiples - Google Patents

Proceso de desbloque en un sistema multiprocesador de ductos multiples

Info

Publication number
MX171836B
MX171836B MX018980A MX1898089A MX171836B MX 171836 B MX171836 B MX 171836B MX 018980 A MX018980 A MX 018980A MX 1898089 A MX1898089 A MX 1898089A MX 171836 B MX171836 B MX 171836B
Authority
MX
Mexico
Prior art keywords
bus
module
function
deblocking
freeing
Prior art date
Application number
MX018980A
Other languages
English (en)
Inventor
Philippe Lallement
Original Assignee
Alcatel Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Nv filed Critical Alcatel Nv
Publication of MX171836B publication Critical patent/MX171836B/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Debugging And Monitoring (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Lock And Its Accessories (AREA)
  • Small-Scale Networks (AREA)

Abstract

La presente invención se refiere a un método para bloquear un sistema multiprocesador, cuyo sistema es del tipo que incluye cuando menos un módulo de procesamiento, cada uno de los cuales está constituído por procesadores conectados a un solo ducto principal, cada uno de cuyos procesadores incluye una celda para manejo de acceso de ducto principal, que emplea dos fases, las cuales comprenden, primero un sistema para asignación de ducto que suministra, durante una primera fase, una señal de resultado (negativo o positivo) para el procesador, del arbitraje de solicitante de acceso expresadas el mismo ciclo por los procesadores de módulo y en segundo un circuito para adoptación o posición de ducto, que proporcioan durante una segunda fase, acceso al ducto de procesador, enviando unaseñal de propiedad de ducto, cuando el resultado es positivo del sistema de asignación durante la primera fase, el método está caracterizado porque comprende asignar a un tablero de desbloque específico, una detencción de bloqueo de módulo y una función de liberación de ducto para el módulo, y en que dicha función de liberación de ducto consisteen enviar una señal de descongestión sencilla, que tiene el efecto de provocar en todos los procesadores del módulo, primero un forzamiento a negativo del resultado de la signación y segundo un forzamiento a la ituación cancelada de la señal de propiedad del ducto.
MX018980A 1988-12-30 1989-12-29 Proceso de desbloque en un sistema multiprocesador de ductos multiples MX171836B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8817506A FR2642246B1 (fr) 1988-12-30 1988-12-30 Procede de deblocage d'un systeme multiprocesseurs multibus

Publications (1)

Publication Number Publication Date
MX171836B true MX171836B (es) 1993-11-18

Family

ID=9373643

Family Applications (1)

Application Number Title Priority Date Filing Date
MX018980A MX171836B (es) 1988-12-30 1989-12-29 Proceso de desbloque en un sistema multiprocesador de ductos multiples

Country Status (12)

Country Link
US (1) US5553247A (es)
EP (1) EP0376249B1 (es)
JP (1) JP2724226B2 (es)
KR (1) KR0137020B1 (es)
CN (1) CN1020814C (es)
AT (1) ATE142803T1 (es)
AU (1) AU630647B2 (es)
CA (1) CA2006936C (es)
DE (1) DE68927157T2 (es)
ES (1) ES2091760T3 (es)
FR (1) FR2642246B1 (es)
MX (1) MX171836B (es)

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US6311255B1 (en) 1999-04-29 2001-10-30 International Business Machines Corporation System and method for selectively restricting access to memory for bus attached unit IDs
WO2002075341A1 (en) * 2001-03-19 2002-09-26 Hitachi, Ltd. Semiconductor device and its test method
DE10136151C2 (de) * 2001-07-25 2003-06-05 Infineon Technologies Ag Multiprozessor-System mit zumindest zwei Mikroprozessoren mit optimaler Ausnutzung der zur Verfügung stehenden Ressourcen
US7130943B2 (en) * 2004-09-30 2006-10-31 Freescale Semiconductor, Inc. Data processing system with bus access retraction
US10470995B2 (en) 2018-02-21 2019-11-12 L'oreal Mascara compositions comprising a bimodal acrylic polymer and anionic, water-dispersible polyester and an aliphatic tackifier
CN109582626B (zh) * 2018-12-03 2021-10-29 郑州云海信息技术有限公司 一种访问总线的方法、装置、设备及可读存储介质
CN112948294B (zh) * 2021-03-19 2024-02-09 北京控制工程研究所 面向SOC的全域并行收发数据的双通道SpaceWire控制器及控制方法

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Also Published As

Publication number Publication date
US5553247A (en) 1996-09-03
CN1044196A (zh) 1990-07-25
JPH02226356A (ja) 1990-09-07
AU4735989A (en) 1990-07-05
KR0137020B1 (ko) 1998-06-15
CN1020814C (zh) 1993-05-19
EP0376249A1 (fr) 1990-07-04
JP2724226B2 (ja) 1998-03-09
DE68927157D1 (de) 1996-10-17
FR2642246B1 (fr) 1991-04-05
ES2091760T3 (es) 1996-11-16
EP0376249B1 (fr) 1996-09-11
FR2642246A1 (fr) 1990-07-27
DE68927157T2 (de) 1997-02-06
CA2006936C (fr) 1999-10-19
CA2006936A1 (fr) 1990-06-30
AU630647B2 (en) 1992-11-05
ATE142803T1 (de) 1996-09-15
KR900010537A (ko) 1990-07-07

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