JPS5733473A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5733473A
JPS5733473A JP10550580A JP10550580A JPS5733473A JP S5733473 A JPS5733473 A JP S5733473A JP 10550580 A JP10550580 A JP 10550580A JP 10550580 A JP10550580 A JP 10550580A JP S5733473 A JPS5733473 A JP S5733473A
Authority
JP
Japan
Prior art keywords
access
given
access request
cpu3
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10550580A
Other languages
Japanese (ja)
Other versions
JPS622343B2 (en
Inventor
Hidehiko Nishida
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10550580A priority Critical patent/JPS5733473A/en
Publication of JPS5733473A publication Critical patent/JPS5733473A/en
Publication of JPS622343B2 publication Critical patent/JPS622343B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To eliminate the useless access time, by just setting the access request to a main memory under the queuing state at the access side of an intermediate buffer memory. CONSTITUTION:An access request given from a CPU3 of the 3rd central processor is given to a buffer access control part 6 while the access requests given from CPU1 and CPU2 of the 1st and 2nd central processors respectively. In such case, an access is requested to an access state monitor part 5 if the fact that the operand of the side to receive an access request is not set to an intermediate buffer memory 1 is decided from the result of an index given to a control table 1-0. In this case, the 1st and 2nd access controllers 3 and 4 are executing the preceding accesses. Accordingly a monitor part 5 transmits a busy signal to the control part 6 to repeal the access request. However, the CPU3 holds this access at a register R3 and thus applies this access again to the part 6.
JP10550580A 1980-07-31 1980-07-31 Memory access control system Granted JPS5733473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10550580A JPS5733473A (en) 1980-07-31 1980-07-31 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10550580A JPS5733473A (en) 1980-07-31 1980-07-31 Memory access control system

Publications (2)

Publication Number Publication Date
JPS5733473A true JPS5733473A (en) 1982-02-23
JPS622343B2 JPS622343B2 (en) 1987-01-19

Family

ID=14409451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10550580A Granted JPS5733473A (en) 1980-07-31 1980-07-31 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5733473A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730168A (en) * 1980-07-29 1982-02-18 Nec Corp Cash memory access system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730168A (en) * 1980-07-29 1982-02-18 Nec Corp Cash memory access system

Also Published As

Publication number Publication date
JPS622343B2 (en) 1987-01-19

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