ATE134070T1 - Verfahren zum herstellen einer abgeschiedenen schicht und verfahren zum herstellen einer halbleitervorrichtung - Google Patents

Verfahren zum herstellen einer abgeschiedenen schicht und verfahren zum herstellen einer halbleitervorrichtung

Info

Publication number
ATE134070T1
ATE134070T1 AT90310500T AT90310500T ATE134070T1 AT E134070 T1 ATE134070 T1 AT E134070T1 AT 90310500 T AT90310500 T AT 90310500T AT 90310500 T AT90310500 T AT 90310500T AT E134070 T1 ATE134070 T1 AT E134070T1
Authority
AT
Austria
Prior art keywords
producing
semiconductor device
deposited layer
electron donative
donative surface
Prior art date
Application number
AT90310500T
Other languages
English (en)
Inventor
Kazuaki C O Canon Kabushi Ohmi
Osamu C O Canon Kabushik Ikeda
Shigeyuki C O Canon Matsumoto
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1250018A external-priority patent/JPH03110840A/ja
Priority claimed from JP1250017A external-priority patent/JPH03111570A/ja
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE134070T1 publication Critical patent/ATE134070T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/107Melt

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
AT90310500T 1989-09-26 1990-09-25 Verfahren zum herstellen einer abgeschiedenen schicht und verfahren zum herstellen einer halbleitervorrichtung ATE134070T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1250018A JPH03110840A (ja) 1989-09-26 1989-09-26 堆積膜形成法
JP1250017A JPH03111570A (ja) 1989-09-26 1989-09-26 堆積膜形成法

Publications (1)

Publication Number Publication Date
ATE134070T1 true ATE134070T1 (de) 1996-02-15

Family

ID=26539605

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90310500T ATE134070T1 (de) 1989-09-26 1990-09-25 Verfahren zum herstellen einer abgeschiedenen schicht und verfahren zum herstellen einer halbleitervorrichtung

Country Status (8)

Country Link
US (1) US6025243A (de)
EP (1) EP0420589B1 (de)
KR (1) KR940006665B1 (de)
AT (1) ATE134070T1 (de)
DE (1) DE69025252T2 (de)
MY (1) MY110288A (de)
PT (1) PT95436B (de)
SG (1) SG59964A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW310461B (de) 1995-11-10 1997-07-11 Matsushita Electric Industrial Co Ltd
JP2002334868A (ja) * 2001-05-10 2002-11-22 Hitachi Kokusai Electric Inc 基板処理装置および半導体装置の製造方法
US6939801B2 (en) * 2001-12-21 2005-09-06 Applied Materials, Inc. Selective deposition of a barrier layer on a dielectric material
JP4592373B2 (ja) * 2004-09-30 2010-12-01 株式会社トリケミカル研究所 導電性モリブデンナイトライドゲート電極膜の形成方法
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP2019145589A (ja) * 2018-02-16 2019-08-29 東芝メモリ株式会社 半導体装置の製造方法
KR102828798B1 (ko) 2018-12-05 2025-07-02 램 리써치 코포레이션 보이드 프리 (void free) 저응력 (low stress) 충진
US12261081B2 (en) 2019-02-13 2025-03-25 Lam Research Corporation Tungsten feature fill with inhibition control
WO2023086298A1 (en) * 2021-11-10 2023-05-19 Entegris, Inc. Molybdenum precursor compounds

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE73869T1 (de) * 1985-05-10 1992-04-15 Gen Electric Verfahren und vorrichtung zum selektiven chemischen aufdampfen.
JPS62281349A (ja) * 1986-05-29 1987-12-07 Seiko Instr & Electronics Ltd 金属パタ−ン膜の形成方法及びその装置
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR940006665B1 (ko) 1994-07-25
DE69025252T2 (de) 1996-07-04
PT95436B (pt) 1997-07-31
EP0420589A2 (de) 1991-04-03
EP0420589A3 (en) 1991-08-21
PT95436A (pt) 1991-05-22
MY110288A (en) 1998-04-30
DE69025252D1 (de) 1996-03-21
US6025243A (en) 2000-02-15
SG59964A1 (en) 1999-02-22
KR910007073A (ko) 1991-04-30
EP0420589B1 (de) 1996-02-07

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Legal Events

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