WO2024150370A1 - 絶縁基板および半導体装置 - Google Patents

絶縁基板および半導体装置 Download PDF

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Publication number
WO2024150370A1
WO2024150370A1 PCT/JP2023/000594 JP2023000594W WO2024150370A1 WO 2024150370 A1 WO2024150370 A1 WO 2024150370A1 JP 2023000594 W JP2023000594 W JP 2023000594W WO 2024150370 A1 WO2024150370 A1 WO 2024150370A1
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WO
WIPO (PCT)
Prior art keywords
circuit pattern
ceramic substrate
outer periphery
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/000594
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English (en)
French (fr)
Japanese (ja)
Inventor
勝彦 近藤
裕児 井本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2023/000594 priority Critical patent/WO2024150370A1/ja
Priority to CN202380090039.4A priority patent/CN120500746A/zh
Priority to JP2024569943A priority patent/JPWO2024150370A1/ja
Priority to DE112023005604.8T priority patent/DE112023005604T5/de
Publication of WO2024150370A1 publication Critical patent/WO2024150370A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof

Definitions

  • This disclosure relates to insulating substrates and semiconductor devices.
  • Patent Document 1 proposes a semiconductor device that can improve the reliability of the connection between the circuit pattern and the semiconductor element.
  • Insulating substrates mounted on semiconductor devices undergo a plating process aimed at soldering the semiconductor element to the circuit pattern formed on the surface of the ceramic substrate contained in the insulating substrate, as well as a plating stripping process.
  • plating is applied to the entire insulating substrate.
  • plating stripping process only the areas necessary for soldering are masked with a resist material, and the plating is dissolved and removed from areas that do not require plating using a stripping solution, after which the plating residue is removed with an air blower.
  • solder reservoir recess is formed on the outer periphery of the circuit pattern, but the solder reservoir recess has only the function of storing the solder material used to join the semiconductor element and the circuit pattern, and does not take into consideration problems caused by plating residue.
  • the present disclosure therefore aims to provide a technology that can suppress deterioration of appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices.
  • the insulating substrate according to the present disclosure comprises a ceramic substrate and a circuit pattern bonded to the surface of the ceramic substrate and on which a semiconductor element is to be mounted, and a recessed portion that does not come into contact with the surface of the ceramic substrate is formed on the back side of the outer periphery of the circuit pattern that is bonded to the ceramic substrate.
  • the stripping solution in the plating stripping process carried out before bonding the circuit pattern to the semiconductor element, the stripping solution is more easily absorbed into the back side of the outer periphery of the circuit pattern, and the air blowing for removing the plating residue is more effectively applied, making it possible to more effectively remove the unnecessary plating residue.
  • This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to a first modification of the third embodiment.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to a second modification of the third embodiment.
  • 13A to 13C are a top view, a cross-sectional view along line AA, and a cross-sectional view along line BB of a semiconductor device according to a fourth embodiment of the present invention, viewed from above a semiconductor element.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 13 is a cross-sectional
  • FIG. 13 is a top view of a part of a semiconductor device according to a first modification of the fourth embodiment, viewed from above a semiconductor element.
  • FIG. 13 is a top view of a part of a semiconductor device according to a second modification of the fourth embodiment, viewed from above a semiconductor element.
  • FIG. 13 is a top view of a part of a semiconductor device according to a third modification of the fourth embodiment, viewed from above a semiconductor element.
  • FIG. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment.
  • the semiconductor device 100 includes a base plate 1, an insulating substrate 2, a semiconductor element 3, a main terminal 4, a resin case 5, and a sealing resin 6.
  • the base plate 1 has a rectangular shape when viewed from above, and is made of a material with relatively high thermal conductivity, such as copper, a copper alloy, aluminum, or an aluminum alloy.
  • the insulating substrate 2 has a front circuit pattern 2a, a ceramic substrate 2b, and a back circuit pattern 2c.
  • the ceramic substrate 2b is made of ceramics such as Al2O3 , AlN , and Si3N4 .
  • the front circuit pattern 2a and the back circuit pattern 2c are made of metals mainly composed of Cu.
  • the front circuit pattern 2a and the back circuit pattern 2c are respectively joined to the front and back surfaces of the ceramic substrate 2b by brazing material (not shown).
  • the front circuit pattern 2a is a circuit pattern on which the semiconductor element 3 is to be mounted, and is selectively patterned. That is, a plurality of front circuit patterns 2a are formed, and the circuits required for the semiconductor device 100 are formed.
  • the semiconductor element 3 is mounted on the front circuit pattern 2a by bonding the back electrode (e.g., collector electrode) of the semiconductor element 3 via a bonding material 7 made of lead-free solder such as Sn-Ag.
  • the semiconductor element 3 is a power semiconductor element made of, for example, Si, SiC, or GaN, and since power semiconductor elements generate high temperatures during operation, it is important to ensure high heat dissipation. Note that although two semiconductor elements 3 are shown in FIG. 1, the number is not limited to two and may be one or more.
  • the main terminal 4 which is mainly composed of Cu, is bonded to the surface electrode (e.g., emitter electrode or gate electrode) of the semiconductor element 3 via a bonding material 7 to form various wiring, thereby forming the circuits required for the semiconductor device 100.
  • the surface electrode e.g., emitter electrode or gate electrode
  • the resin case 5 is formed into a rectangular frame shape when viewed from above, using a high heat resistant resin such as PPS.
  • the resin case 5 is fixed to the outer periphery of the base plate 1 with an adhesive (not shown) or the like so as to surround the circuit including the semiconductor element 3.
  • the inside of the resin case 5 is filled with a sealing resin 6 such as an epoxy resin, protecting the circuit including the semiconductor element 3.
  • the manufacturing process for the insulating substrate 2 includes a plating process for soldering the surface circuit pattern 2a to the semiconductor element 3, and a plating stripping process.
  • plating is applied to the entire insulating substrate 2.
  • the plating stripping process only the areas necessary for soldering are masked with a resist material, and in areas that do not require plating, the plating is dissolved and removed with a stripping solution, and the plating residue is then removed with an air blower.
  • a recessed portion 8 that does not come into contact with the surface of the ceramic substrate 2b is formed on the back side of the outer periphery of the front circuit pattern 2a that is joined to the ceramic substrate 2b.
  • the recessed portion 8 is formed around the entire periphery of the front circuit pattern 2a.
  • the recessed portion 8 is provided as an opening larger than the small sagging portion in the area where the sagging portion is formed, which allows sufficient penetration of the plating remover solution to the back side of the outer periphery of the front circuit pattern 2a, and improves the air blowing effect. This makes it possible to reduce plating residue.
  • the semiconductor device 100 includes an insulating substrate 2, a semiconductor element 3 mounted on the surface of the surface circuit pattern 2a, and a base plate 1 joined to the back side of the ceramic substrate 2b.
  • the insulating substrate 2 also includes a ceramic substrate 2b and a surface circuit pattern 2a that is bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted.
  • a recessed portion 8 that does not come into contact with the surface of the ceramic substrate 2b is formed on the back side of the outer periphery of the surface circuit pattern 2a that is bonded to the ceramic substrate 2b.
  • the stripping solution is more easily absorbed into the back side of the outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue.
  • This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 100.
  • FIG. 2 is a cross-sectional view of the semiconductor device 200 according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
  • the recessed portion 8 is not formed in the surface circuit pattern 2a, but the recessed portion 9 is formed in the ceramic substrate 2b.
  • the recessed portion 9 is formed so as to be recessed downward in a portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a. Specifically, the recessed portion 9 is formed from a portion of the ceramic substrate 2b facing the entire periphery of the surface circuit pattern 2a toward the outer periphery. Due to the recessed portion 9 being formed, the outer periphery of the surface circuit pattern 2a does not come into contact with the surface of the ceramic substrate 2b.
  • the recessed portion 9 is provided as an opening larger than the sagging portion in the portion adjacent to the portion where the minute sagging portion is formed, which allows sufficient penetration of the plating remover solution to the back side of the outer periphery of the front circuit pattern 2a and improves the air blowing effect. This makes it possible to reduce plating residue.
  • the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted.
  • a recessed portion 9 recessed downward is formed in a portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a.
  • the stripping solution is more likely to penetrate the back side of the outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue.
  • This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 200.
  • Fig. 3 is a cross-sectional view of the semiconductor device 300 according to the third embodiment. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof will be omitted.
  • the recessed portions 8 and 9 are not formed, and the outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10 in which the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b toward the front surface on which the semiconductor element 3 is mounted.
  • the tapered shape 10 is formed around the entire periphery of the surface circuit pattern 2a.
  • the outer periphery of the surface circuit pattern 2a By forming the outer periphery of the surface circuit pattern 2a into a tapered shape 10, the outer periphery of the surface circuit pattern 2a faces upward, making it easier for the stripping solution to penetrate the entire outer periphery of the surface circuit pattern 2a, and improving the airflow for removing plating residue, making it possible to more effectively remove unnecessary plating residue.
  • the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b, on which the semiconductor element 3 is to be mounted.
  • the outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10 in which the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b toward the front surface on which the semiconductor element 3 is to be mounted.
  • the stripping solution is more likely to penetrate the entire outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue.
  • This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 300.
  • Fig. 4 is a cross-sectional view of a semiconductor device 400 according to a first modification of the third embodiment.
  • Fig. 5 is a cross-sectional view of a semiconductor device 500 according to a second modification of the third embodiment.
  • the tapered shape 11 of the outer periphery of the surface circuit pattern 2a may be formed in a curved shape.
  • the tapered shape 12 of the outer periphery of the surface circuit pattern 2a may be formed in a stepped shape. In these cases, the same effect as in the third embodiment can be obtained.
  • Fig. 6(a) is a top view of the semiconductor device 600 according to the fourth embodiment, viewed from above the semiconductor element 3.
  • Fig. 6(b) is a cross-sectional view taken along line A-A in Fig. 6(a)
  • Fig. 6(c) is a cross-sectional view taken along line B-B in Fig. 6(a). Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and description thereof will be omitted.
  • cutout portions 13 are formed in place of the recessed portions 8 and 9 and the tapered shapes 10, 11, and 12.
  • a plurality of cutout portions 13 are formed continuously around the entire periphery of the outer periphery of the surface circuit pattern 2a.
  • the cutout portions 13 have a rectangular shape when viewed from above, and two are formed on each side of the surface circuit pattern 2a.
  • the cutout portion 13 is formed to the same thickness as the thickness of each surface circuit pattern 2a. Also, as shown in Figures 6(a) and (b), the portion of each surface circuit pattern 2a without the cutout portion 13 has the same width d2 as the conventional structure without the cutout portion 13.
  • the width of one side at the outer periphery of each surface circuit pattern 2a is d2, and if plating residue with a length equivalent to d2 remains, there is a possibility that the plating residue will flow across the length d1 between adjacent surface circuit patterns 2a during the manufacture of the semiconductor device, and there is a risk that the plating residue will cause insulation defects such as short circuits between the surface circuit patterns 2a.
  • d2 ⁇ d1.
  • the width d3 of one side at the outer periphery of each surface circuit pattern 2a which is the length between adjacent cutout portions 13 on the outer periphery of each surface circuit pattern 2a, is formed to be sufficiently shorter than the length d1 between adjacent surface circuit patterns 2a (d3 ⁇ d1). Therefore, even if plating residue having a length equivalent to d3 remains and flows across the length d1 between the surface circuit patterns 2a during the manufacture of the semiconductor device 600, it is possible to prevent the plating residue from coming into contact with the adjacent surface circuit patterns 2a.
  • the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a that is bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted.
  • a plurality of continuous cutout portions 13 are formed on the outer periphery of the surface circuit pattern 2a. Furthermore, each cutout portion 13 is formed in a rectangular shape when viewed from above.
  • Fig. 7 is a top view of a portion of a semiconductor device 700 according to modified example 1 of the fourth embodiment, viewed from above the semiconductor element 3.
  • Fig. 8 is a top view of a portion of a semiconductor device 800 according to modified example 2 of the fourth embodiment, viewed from above the semiconductor element 3.
  • Fig. 9 is a top view of a portion of a semiconductor device 900 according to modified example 3 of the fourth embodiment, viewed from above the semiconductor element 3.
  • each cutout 14 may be formed in a triangular shape when viewed from above.
  • each cutout 15 may be formed in a stepped shape when viewed from above.
  • each cutout 16 may be formed in an arc shape when viewed from above. In these cases, the same effect as in embodiment 4 can be obtained.
  • each embodiment can be freely combined, modified, or omitted as appropriate.

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PCT/JP2023/000594 2023-01-12 2023-01-12 絶縁基板および半導体装置 Ceased WO2024150370A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2023/000594 WO2024150370A1 (ja) 2023-01-12 2023-01-12 絶縁基板および半導体装置
CN202380090039.4A CN120500746A (zh) 2023-01-12 2023-01-12 绝缘基板及半导体装置
JP2024569943A JPWO2024150370A1 (https=) 2023-01-12 2023-01-12
DE112023005604.8T DE112023005604T5 (de) 2023-01-12 2023-01-12 Isoliertes Substrat und Halbleitervorrichtung

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Application Number Priority Date Filing Date Title
PCT/JP2023/000594 WO2024150370A1 (ja) 2023-01-12 2023-01-12 絶縁基板および半導体装置

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WO2024150370A1 true WO2024150370A1 (ja) 2024-07-18

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PCT/JP2023/000594 Ceased WO2024150370A1 (ja) 2023-01-12 2023-01-12 絶縁基板および半導体装置

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CN (1) CN120500746A (https=)
DE (1) DE112023005604T5 (https=)
WO (1) WO2024150370A1 (https=)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004080063A (ja) * 1996-08-27 2004-03-11 Dowa Mining Co Ltd 高信頼性半導体用基板
JP2007311527A (ja) * 2006-05-18 2007-11-29 Mitsubishi Materials Corp パワーモジュール用基板およびパワーモジュール用基板の製造方法並びにパワーモジュール
JP2009158611A (ja) * 2007-12-25 2009-07-16 Kyocera Corp 回路基板及びこれを用いたパッケージ並びに電子装置
JP2014027221A (ja) * 2012-07-30 2014-02-06 Kyocera Corp 回路基板およびそれを用いた電子装置
JP2015028998A (ja) * 2013-07-30 2015-02-12 株式会社豊田自動織機 半導体装置
JP2015070107A (ja) * 2013-09-30 2015-04-13 三菱電機株式会社 半導体装置およびその製造方法
WO2016098431A1 (ja) * 2014-12-18 2016-06-23 三菱電機株式会社 絶縁回路基板、パワーモジュールおよびパワーユニット
JP2020161842A (ja) * 2015-09-28 2020-10-01 株式会社東芝 回路基板および半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004080063A (ja) * 1996-08-27 2004-03-11 Dowa Mining Co Ltd 高信頼性半導体用基板
JP2007311527A (ja) * 2006-05-18 2007-11-29 Mitsubishi Materials Corp パワーモジュール用基板およびパワーモジュール用基板の製造方法並びにパワーモジュール
JP2009158611A (ja) * 2007-12-25 2009-07-16 Kyocera Corp 回路基板及びこれを用いたパッケージ並びに電子装置
JP2014027221A (ja) * 2012-07-30 2014-02-06 Kyocera Corp 回路基板およびそれを用いた電子装置
JP2015028998A (ja) * 2013-07-30 2015-02-12 株式会社豊田自動織機 半導体装置
JP2015070107A (ja) * 2013-09-30 2015-04-13 三菱電機株式会社 半導体装置およびその製造方法
WO2016098431A1 (ja) * 2014-12-18 2016-06-23 三菱電機株式会社 絶縁回路基板、パワーモジュールおよびパワーユニット
JP2020161842A (ja) * 2015-09-28 2020-10-01 株式会社東芝 回路基板および半導体装置

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DE112023005604T5 (de) 2025-11-06
CN120500746A (zh) 2025-08-15

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