WO2024111058A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2024111058A1
WO2024111058A1 PCT/JP2022/043190 JP2022043190W WO2024111058A1 WO 2024111058 A1 WO2024111058 A1 WO 2024111058A1 JP 2022043190 W JP2022043190 W JP 2022043190W WO 2024111058 A1 WO2024111058 A1 WO 2024111058A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
metal block
lead electrode
semiconductor chip
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/043190
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English (en)
French (fr)
Japanese (ja)
Inventor
浩二 田中
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to DE112022008031.0T priority Critical patent/DE112022008031T5/de
Priority to JP2024559772A priority patent/JPWO2024111058A1/ja
Priority to US18/873,591 priority patent/US20250372496A1/en
Priority to PCT/JP2022/043190 priority patent/WO2024111058A1/ja
Priority to CN202280101756.8A priority patent/CN120202541A/zh
Publication of WO2024111058A1 publication Critical patent/WO2024111058A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 discloses a structure in which a pad portion and a conductive spacer are bonded to a semiconductor device.
  • the pad portion and the spacer are bonded to each other by, for example, ultrasonic bonding.
  • One method for joining lead electrodes to a semiconductor chip is to, for example, eject molten metal onto one main surface of the semiconductor chip.
  • Another method involves placing a bonding material and lead electrodes on a semiconductor chip that has already been joined to a circuit pattern on an insulating substrate, and then reflowing the material.
  • This method of joining a lead electrode to a semiconductor chip has a larger bonding area than a method of forming a circuit by joining a metal wire to a semiconductor chip. This allows for the expected increase in current and longer life.
  • the present disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress damage to a semiconductor chip during ultrasonic bonding.
  • the semiconductor device disclosed herein comprises a semiconductor chip, a metal block having a first surface and a second surface opposite the first surface, the first surface being joined to the semiconductor chip with a bonding material, and a lead electrode joined to the second surface of the metal block, and a plurality of projections and recesses are formed on the surface of the lead electrode opposite the surface joined to the metal block.
  • the method of manufacturing a semiconductor device includes bonding a semiconductor chip to a first surface of a metal block having a first surface and a second surface opposite the first surface with a bonding material, and then applying ultrasonic vibrations to the surface of a lead electrode opposite the metal block to ultrasonically bond the second surface of the metal block to the lead electrode.
  • ultrasonic bonding is performed between the metal block and the lead electrode, thereby suppressing damage to the semiconductor chip during ultrasonic bonding.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a first embodiment; 1 is a plan view of a semiconductor device according to a first embodiment; 11A to 11C are diagrams illustrating other examples of ultrasonic bonding marks.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment.
  • Fig. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment.
  • Fig. 2 is a plan view of the semiconductor device 100 according to the first embodiment.
  • Fig. 1 shows a typical configuration of a semiconductor chip 20, a metal block 24, and a joint portion of a lead electrode of the semiconductor device 100. Note that the semiconductor device 100 is illustrated in a simplified manner in Fig. 1, and for example, wires, which are signal lines electrically connected to the semiconductor chip 20, signal terminals, etc. are omitted.
  • the semiconductor device 100 is, for example, a power semiconductor device.
  • a case 10 is provided on a base plate 12.
  • the base plate 12 is made of a material with excellent thermal conductivity, such as an aluminum alloy or copper.
  • An insulating substrate 14 is bonded to the area of the upper surface of the base plate 12 surrounded by the case 10 with a bonding material such as solder or soft solder.
  • the insulating substrate 14 has an insulating layer made of a ceramic with excellent thermal conductivity, such as aluminum nitride or silicon nitride, or a resin, and a circuit pattern 16 provided on both sides of the insulating layer.
  • the circuit pattern 16 is made of an aluminum alloy or copper. In FIG. 1, the circuit pattern 16 provided on the upper surface of the insulating layer of the insulating substrate 14 is shown.
  • the semiconductor chip 20 has a substrate, an electrode 20a provided on the top surface of the substrate, and an electrode 20b provided on the bottom surface of the substrate.
  • the electrode 20b of the semiconductor chip 20 is bonded to the circuit pattern 16 using a bonding material 18.
  • the bonding material 18 is, for example, solder, soft solder, etc.
  • the semiconductor chip 20 is, for example, an IGBT, a diode, a reverse conducting IGBT, etc. made of silicon (Si).
  • the semiconductor chip 20 may be a MOSFET or a Schottky diode made of a material with a larger band gap than Si, such as silicon carbide (SiC) or gallium nitride (GaN).
  • the number of semiconductor chips 20 on the insulating substrate 14 is not limited. The required number or types of semiconductor chips 20 may be mounted depending on the application of the semiconductor device 100.
  • the metal block 24 has a first surface and a second surface opposite to the first surface.
  • the first surface is bonded to the electrode 20a of the semiconductor chip 20 with a bonding material 22.
  • the bonding material 22 is solder, soft solder, or the like.
  • the metal block 24 is formed from a metal such as copper or aluminum that has excellent thermal conductivity and low electrical resistance.
  • the metal block 24 is not limited to this and may be made of any metal that has the desired characteristics.
  • the lower surface of the lead electrode 26, which is made of metal, is joined to the second surface of the metal block 24.
  • the lead electrode 26 and the metal block 24 are joined by ultrasonic bonding.
  • the metal block 24 and the lead electrode 26 are joined without any bonding material.
  • a plurality of irregularities 50 are formed on the surface of the lead electrode 26 opposite to the surface joined to the metal block 24.
  • the multiple irregularities 50 are ultrasonic bonding marks.
  • the multiple irregularities 50 are formed in a position of the lead electrode 26 that overlaps with the metal block 24 in a planar view.
  • the ultrasonic bonding marks are also called ultrasonic vibration application marks.
  • the shape of the multiple unevenness 50 which is the ultrasonic bonding marks, varies depending on the tip shape and vibration direction of the ultrasonic vibration tool 60. For example, by applying a reciprocating vibration in a single direction to the upper surface of the lead electrode 26, an application mark of continuous parallel unevenness can be formed as the multiple unevenness 50, as shown in FIG. 2.
  • multiple continuous square pyramids may be formed as the multiple unevenness 50.
  • FIG. 3 is a diagram explaining another example of ultrasonic bonding marks.
  • multiple unevennesses 50a are arranged in two directions.
  • the multiple unevennesses 50a are formed in an area of, for example, 4 mm x 8 mm.
  • the width of each unevenness included in the multiple unevennesses 50a is, for example, about 0.1 mm to 10 mm.
  • Multiple metal blocks 24 may be bonded to one semiconductor chip 20.
  • the number of ultrasonic bonding marks formed corresponds to the number of metal blocks 24.
  • two metal blocks 24 are bonded to one semiconductor chip 20.
  • the lead electrode 26 may be formed by extending an external electrode 28 previously inserted into the case 10 onto the semiconductor chip 20.
  • the lead electrode 26 may be joined to the external electrode 28 previously provided on the case 10 by solder bonding, laser welding, ultrasonic bonding, etc.
  • a portion of the lead electrode 26 may be connected to the circuit pattern 16 by ultrasonic bonding, solder bonding, laser welding, etc. to form a circuit.
  • one lead electrode 26 may be joined across multiple metal blocks 24 on multiple semiconductor chips 20.
  • the assembly procedure of the semiconductor device 100 in this embodiment is shown below.
  • the circuit pattern 16 of the insulating substrate 14 and the semiconductor chip 20, and the semiconductor chip 20 and the first surface of the metal block 24 are bonded with bonding materials 18, 22 such as plate solder, solder paste, soft solder, etc.
  • the bonding materials 18, 22 are first mounted on the circuit pattern 16 and the semiconductor chip 20.
  • solder is often used as the bonding materials 18, 22.
  • the bonding materials 18, 22, such as solder paste may be applied by screen printing or may be applied using a dispenser, etc.
  • the semiconductor device 100 is heated to a temperature exceeding the melting points of the bonding materials 18, 22, thereby performing bonding.
  • the metal block 24 and the semiconductor chip 20 may be bonded simultaneously in the process of bonding the semiconductor chip 20 to the circuit pattern 16.
  • the semiconductor chip 20 and the metal block 24 may be bonded after bonding the semiconductor chip 20 to the circuit pattern 16.
  • the bonding material 22 may be placed on the semiconductor chip 20 by screen printing or dispensing, etc., and the metal block 24 may be placed on the bonding material 22, and then the bonding material 22 may be locally heated by laser heating or hot air heating, etc. to bond them. This makes it possible to prevent the bonding material 18 from melting again.
  • the case 10 is bonded to the base plate 12.
  • a silicone-based or epoxy-based adhesive is first applied to the bonding surface of the case 10 with the base plate 12.
  • the case 10 is fitted to the base plate 12 to which the semiconductor chip 20 and insulating substrate 14 are bonded, and a load is applied to the case 10 to bring the case 10 and base plate 12 into close contact.
  • the case 10 and base plate 12 may be fastened together with tapping screws or the like.
  • the adhesive may be heated and solidified while the case 10 and base plate 12 are fixed together with a clamping jig or the like.
  • a lead electrode 26 is placed on the second surface of the metal block 24.
  • ultrasonic vibrations are applied to the surface of the lead electrode 26 opposite the metal block 24, ultrasonically bonding the second surface of the metal block 24 and the lead electrode 26.
  • Pressure is applied to the lead electrode 26 from the surface opposite the surface in contact with the metal block 24 by an ultrasonic vibration tool 60.
  • the lead electrode 26 and metal block 24 are bonded by applying ultrasonic vibrations while being pressurized with a constant load.
  • the control electrodes on the semiconductor chip 20 are connected to external signal terminals with wires using ultrasonic bonding.
  • wires Generally, aluminum, which has high thermal and electrical conductivity, is often used for the wires.
  • the inside of the case 10 is sealed with a sealing resin.
  • Silicone gel or epoxy resin is often used as the sealing resin.
  • any material that has the desired physical properties such as elastic modulus, heat resistance, adhesiveness, and linear expansion coefficient can be used as the sealing resin.
  • the semiconductor device 100 is placed in a curing oven or the like to harden the sealing resin, and the shape of the semiconductor device 100 is completed after the necessary hardening is carried out. After that, inspections of electrical characteristics, etc. are carried out, and the semiconductor device 100 is completed.
  • the metal block 24 between the semiconductor chip 20 and the lead electrode 26.
  • damage to the semiconductor chip 20 during ultrasonic bonding can be suppressed.
  • the upper surface of the semiconductor chip 20 does not become the bonding portion of the ultrasonic bonding, damage to the semiconductor chip 20 can be suppressed even if ultrasonic vibration is applied while pressure is applied to the lead electrode 26.
  • ultrasonic bonding can be applied when forming a circuit between the lead electrode 26 and the semiconductor chip 20, and there is no need to heat the entire semiconductor device 100.
  • the semiconductor chip 20 may be formed of a wide band gap semiconductor.
  • the wide band gap semiconductor is, for example, silicon carbide, a gallium nitride material, or diamond. According to this embodiment, even when the semiconductor chip 20 is formed of a wide band gap semiconductor and a high current flows, it is possible to suppress a decrease in bonding strength and a decrease in the reliability of the semiconductor device 100.
  • FIG. 4 is a cross-sectional view of a semiconductor device 200 according to the second embodiment.
  • the semiconductor device 200 differs from the semiconductor device 100 according to the first embodiment in the structure of the metal block 224 and the lead electrode 226.
  • the other configurations are the same as those of the first embodiment.
  • a fitting portion that fits with the lead electrode 226 is formed on the second surface of the metal block 224.
  • a convex portion 224a is formed on the second surface of the metal block 224
  • a concave portion 226a is formed on the lower surface of the lead electrode 226.
  • the metal block 224 and the lead electrode 226 are ultrasonically bonded.
  • the flat portion of the upper surface of the convex portion 224a of the metal block 224 and the flat bottom portion of the concave portion 226a of the lead electrode 226 are ultrasonically bonded.
  • the metal block 224 and the lead electrode 226 are fitted together, so that the lead electrode 226 can be easily positioned in the horizontal direction even if the lead electrode 226 is not fixed before bonding.
  • the horizontal positioning accuracy of the lead electrode 226 can be improved, and the semiconductor device 200 can be manufactured stably.
  • the shapes of the convex portion 224a and the concave portion 226a are not limited. Also, a concave portion may be formed in the metal block 224, and a convex portion may be formed in the lead electrode 226.
  • Embodiment 3. 5 is a cross-sectional view of a semiconductor device 300 according to the third embodiment.
  • the semiconductor device 300 differs from the semiconductor device 100 of the first embodiment in the structure of the lead electrode 326.
  • the other configurations are similar to those of the first embodiment.
  • a recess 327 is formed on the surface of the lead electrode 326 opposite to the surface bonded to the metal block 24.
  • a plurality of irregularities 50 which are ultrasonic bonding marks, are formed on the bottom surface of the recess 327.
  • a recess 327 is formed on the top surface of the lead electrode 326, which makes it possible to suppress scattering of metal chips that occurs when ultrasonically bonding the lead electrode 26 and the metal block 24. This allows for stable manufacture of the semiconductor device 300. It is preferable that the depth of the recess 327 is greater than the maximum depth of the multiple asperities 50. This enhances the effect of suppressing scattering of metal chips.
  • the maximum depth of the multiple asperities 50 is, for example, 0.5 mm to 0.8 mm.
  • the width of the recess 327 may be greater than the width of the region of the lead electrode 326 that contacts the metal block 24.
  • the area of the recess 327 may be greater than the area of the region of the lead electrode 326 that contacts the metal block 24. This ensures a sufficient area for the ultrasonic bonding portion even when the recess 327 is formed.
  • Embodiment 4. 6 is a cross-sectional view of a semiconductor device 400 according to a fourth embodiment.
  • the semiconductor device 400 differs from the semiconductor device 100 of the first embodiment in the structure of a metal block 424.
  • the other configurations are the same as those of the first embodiment.
  • the metal block 424 has a copper layer 424a bonded to the semiconductor chip 20 with a bonding material 22, and an aluminum layer 424b ultrasonically bonded to the lead electrode 26.
  • the metal block 424 is, for example, a clad material formed by applying pressure to the surfaces of a copper material and an aluminum material to perform roll bonding.
  • the soft aluminum layer 424b is present in a portion of the metal block 424, which can reduce damage to the semiconductor chip 20 caused by ultrasonic vibrations when ultrasonically bonding the lead electrode 26 and the metal block 424.
  • aluminum material is less likely to form intermetallic compounds with the bonding material 22 such as solder.
  • the copper layer 424a is present on the surface where the semiconductor chip 20 is bonded with the bonding material 22, which can easily bond the metal block 424 to the semiconductor chip 20. Therefore, the semiconductor device 400 can be manufactured stably.
  • the metal block 424 only needs to have the copper layer 424a and the aluminum layer 424b. For example, another metal layer may be provided between the copper layer 424a and the aluminum layer 424b.
  • Embodiment 5. 7 is a cross-sectional view of a semiconductor device 500 according to a fourth embodiment.
  • the thickness b of the metal block 524 of the semiconductor device 500 is equal to or greater than the thickness of the portion of the lead electrode 26 that is joined to the metal block 524.
  • the other configurations are the same as those of the first embodiment.
  • the thickness b of the metal block 524 is equal to or greater than 0.6 mm.
  • the metal block 524 that is thicker than the lead electrode 26 is between the semiconductor chip 20 and the lead electrode 26. This makes it possible to further suppress damage to the semiconductor chip 20 when ultrasonic vibration is applied to the lead electrode 26 while pressure is being applied thereto. Therefore, the semiconductor device 500 can be stably manufactured.

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  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
PCT/JP2022/043190 2022-11-22 2022-11-22 半導体装置および半導体装置の製造方法 Ceased WO2024111058A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE112022008031.0T DE112022008031T5 (de) 2022-11-22 2022-11-22 Halbleitervorrichtung und Verfahren für eine Fertigung einer Halbleitervorrichtung
JP2024559772A JPWO2024111058A1 (https=) 2022-11-22 2022-11-22
US18/873,591 US20250372496A1 (en) 2022-11-22 2022-11-22 Semiconductor device and method for manufacturing semiconductor device
PCT/JP2022/043190 WO2024111058A1 (ja) 2022-11-22 2022-11-22 半導体装置および半導体装置の製造方法
CN202280101756.8A CN120202541A (zh) 2022-11-22 2022-11-22 半导体装置及半导体装置的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/043190 WO2024111058A1 (ja) 2022-11-22 2022-11-22 半導体装置および半導体装置の製造方法

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WO2024111058A1 true WO2024111058A1 (ja) 2024-05-30

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JP (1) JPWO2024111058A1 (https=)
CN (1) CN120202541A (https=)
DE (1) DE112022008031T5 (https=)
WO (1) WO2024111058A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088030A (ja) * 2005-09-20 2007-04-05 Fuji Electric Holdings Co Ltd 半導体装置
JP2009105267A (ja) * 2007-10-24 2009-05-14 Fuji Electric Device Technology Co Ltd 半導体装置およびその製造方法
JP2013197560A (ja) * 2012-03-23 2013-09-30 Hitachi Ltd パワー半導体モジュール
JP2018190930A (ja) * 2017-05-11 2018-11-29 三菱電機株式会社 パワー半導体モジュール及びその製造方法並びに電力変換装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245171A (ja) * 2005-03-02 2006-09-14 Toshiba Corp 電子部品モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088030A (ja) * 2005-09-20 2007-04-05 Fuji Electric Holdings Co Ltd 半導体装置
JP2009105267A (ja) * 2007-10-24 2009-05-14 Fuji Electric Device Technology Co Ltd 半導体装置およびその製造方法
JP2013197560A (ja) * 2012-03-23 2013-09-30 Hitachi Ltd パワー半導体モジュール
JP2018190930A (ja) * 2017-05-11 2018-11-29 三菱電機株式会社 パワー半導体モジュール及びその製造方法並びに電力変換装置

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CN120202541A (zh) 2025-06-24
US20250372496A1 (en) 2025-12-04
JPWO2024111058A1 (https=) 2024-05-30
DE112022008031T5 (de) 2025-11-06

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