WO2024027357A1 - 场截止型绝缘栅双极晶体管及其制造方法 - Google Patents

场截止型绝缘栅双极晶体管及其制造方法 Download PDF

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WO2024027357A1
WO2024027357A1 PCT/CN2023/101143 CN2023101143W WO2024027357A1 WO 2024027357 A1 WO2024027357 A1 WO 2024027357A1 CN 2023101143 W CN2023101143 W CN 2023101143W WO 2024027357 A1 WO2024027357 A1 WO 2024027357A1
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region
field
layer
conductivity type
bipolar transistor
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PCT/CN2023/101143
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English (en)
French (fr)
Inventor
王万
肖魁
卞铮
柴晨凯
杨翔宇
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无锡华润上华科技有限公司
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Publication of WO2024027357A1 publication Critical patent/WO2024027357A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a field-stop insulated gate bipolar transistor, and also relates to a manufacturing method of a field-stop insulated gate bipolar transistor.
  • Insulated Gate Bipolar Transistor as a bipolar device, combines the working mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the working mechanism of bipolar transistor, combining the advantages of both. It is an improved power device.
  • IGBTs are voltage-controlled devices and have high gain under large currents; compared with MOSFETs, IGBTs can withstand higher voltages, and have lower conduction voltage and lower power consumption under large currents.
  • IGBT has experienced three types of structures on the substrate: PT (punch-through), NPT (non-punch-through) and FS (field-stop).
  • the forward blocking withstand voltage is an important parameter, and the industry hopes to improve the device withstand voltage on the premise that other parameters can also meet the needs.
  • a field stop type insulated gate bipolar transistor including a drift region, a front structure and a back structure.
  • the back structure includes: an electrode layer; a collector area located on the electrode layer and having a second conductivity type; a field stop layer , is located on the collector area and has the first conductivity type, and the drift area is located on the field stop layer; wherein a gap is formed in the collector area and the field stop layer to form a gap area, and the gap area Having a first conductivity type, the doping concentration of the notch region is less than the doping concentration of the field stop layer, the drift region has a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivities type.
  • a gap is opened in the collector region and field stop layer on the back of the device.
  • the depletion region continues to extend at the gap, but at the same time it is blocked by the field stop layers on both sides of the gap and does not penetrate.
  • the notch area not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thus further improving Device withstand voltage.
  • the notch region is part of the drift region.
  • the electrode layer is a metal electrode.
  • the width of the notched region is no greater than 0.4 microns.
  • the width of the notch area is 0.2-0.3 microns.
  • the front-side structure includes: a trench gate structure extending downward into the drift region; a second conductivity type well region located on both sides of the trench gate structure; and an emitter region located in the On both sides of the trench gate structure and in the second conductivity type well region; an emitter electrode is located on the emitter region and is electrically connected to the emitter region.
  • the trench gate structure includes a gate dielectric layer located on the inner wall of the trench, and a gate electrode located in the trench and surrounded by the gate dielectric layer; the field-stop insulated gate bipolar transistor further Includes an insulating dielectric layer located on the gate.
  • a method for manufacturing a field-stop insulated gate bipolar transistor including:
  • the drift region has a first conductivity type; an injection blocking structure is formed on the back side of the drift region; the back side of the drift region is the side opposite to the IGBT front-side structure; by The ion implantation process forms a collector region and a field stop layer on the back side of the drift region, and the injected ions at the injection blocking structure are blocked to form a gap region; the field stop layer is located between the collector region and the drift region, so The collector region has a second conductivity type, and the field stop layer has a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; after removing the implant barrier structure, the crystal The back side of the circle forms the electrode layer.
  • the above-mentioned method of manufacturing a field-stop insulated gate bipolar transistor opens a gap in the collector region and field-stop layer on the back of the device.
  • the depletion region continues to extend at the gap, but is blocked by the field-stop layers on both sides of the gap. It does not penetrate the notch area, which not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thereby further improving the device withstand voltage.
  • the width of the notched region is no greater than 0.4 microns.
  • the width of the notch area is 0.2-0.3 microns.
  • a method for manufacturing a field-stop insulated gate bipolar transistor including: obtaining a wafer with a drift region and an IGBT front structure; the drift region has a first conductivity type; forming a first light on the back of the drift region through photolithography Resist layer; the back side of the drift area is the side opposite to the front structure of the IGBT; using the first photoresist layer as an injection barrier layer, a first current collector is formed on the back side of the drift area through an ion implantation process area and the first field cutoff layer, the A field stop layer is located between the first collector area and the drift area; the first photoresist layer is removed and then photolithographed again to form a second photoresist layer on the back of the drift area.
  • the photoresist layer partially overlaps the position where the first photoresist layer is formed; using the second photoresist layer as an injection barrier layer, a second collector region and a second collector region are formed on the back side of the drift region through an ion implantation process.
  • a second field stop layer the second field stop layer is located between the second collector region and the drift region; after removing the second photoresist layer, an electrode layer is formed on the back of the wafer; wherein , a gap region is formed between the first collector region and the second collector region, and between the first field stop layer and the second field stop layer due to ion implantation being blocked; the first collector region and The second collector region has a second conductivity type, the first field stop layer and the second field stop layer have a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types.
  • the above-mentioned method of manufacturing a field-stop insulated gate bipolar transistor opens a gap in the collector region and field-stop layer on the back of the device.
  • the depletion region continues to extend at the gap, but is blocked by the field-stop layers on both sides of the gap. It does not penetrate the notch area, which not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thereby further improving the device withstand voltage.
  • the gap is formed in the area where the photoresist overlaps. The photoresist area formed twice is larger to avoid the photoresist area being too small and falling off, affecting the product yield.
  • the width of the notched region is no greater than 0.4 microns.
  • the width of the notch area is 0.2-0.3 microns.
  • Figure 1 is a schematic cross-sectional structural diagram of a field-stop insulated gate bipolar transistor according to an embodiment
  • Figure 2 is the simulation results of device withstand voltage under different gap widths
  • Figure 3 is a flow chart of a manufacturing method of a field-stop insulated gate bipolar transistor according to an embodiment
  • Figure 4 is a schematic cross-sectional view of the device structure after step S320 is completed in an embodiment of manufacturing an IGBT using the method shown in Figure 3;
  • Figure 5 is a flow chart of a manufacturing method of a field-stop insulated gate bipolar transistor according to another embodiment
  • Figure 6a is a schematic cross-sectional view of the device structure after step S530 is completed in an embodiment of manufacturing an IGBT using the method shown in Figure 5;
  • Figure 6b is a schematic cross-sectional view of the device structure after step S550 is completed in an embodiment of manufacturing an IGBT using the method shown in Figure 5.
  • Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant passes as the implant proceeds. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the present disclosure.
  • P+ type simply represents P type with heavy doping concentration
  • P type represents medium doping concentration
  • P-type with doping concentration P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type N-type with medium doping concentration
  • N-type represents lightly doped concentration.
  • FIG. 1 is a schematic cross-sectional structural diagram of a field-stop insulated gate bipolar transistor according to an embodiment, including a front structure, a back structure and a first conductivity type drift region 20 .
  • the backside structure includes a field stop layer 312, a collector region 322, and an electrode layer 324 (an electrode serving as a collector).
  • the collector region 322 is located on the electrode layer 324 and has the second conductivity type.
  • Field stop layer 312 is located on collector region 322 and has a first conductivity type.
  • Drift region 20 is located on field stop layer 312 .
  • the collector area 322 and the field stop layer 312 are formed with a notch 23 to form a notch area.
  • the notch area has the first conductivity type, and the doping concentration of the notch area is smaller than the doping concentration of the field stop layer 312 .
  • the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type is N-type. .
  • a gap 23 is opened in the collector region 322 and the field stop layer 312 on the back of the device.
  • the depletion region continues to extend at the gap 23, but is also affected by the field stop layers 312 on both sides of the gap 23.
  • the blocking effect prevents the penetration of the notch area, which not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thereby further improving the device withstand voltage.
  • the notch region is part of the drift region 20 .
  • the doping concentration of the entire drift region 20 may not be exactly the same.
  • the notch 23 is in direct contact with the electrode layer 324 .
  • the notch 23 may not completely penetrate the current collection area 322 , that is, a certain thickness of the current collection area 322 remains at the bottom of the notch 23 , and the notch 23 and the electrode layer 324 are separated by the remaining current collection area 322 . open.
  • the notch region penetrates the field stop layer 312 and at least penetrates part of the collector region 322 .
  • the electrode layer 324 is a metal electrode.
  • Figure 2 is the simulation result of the device withstand voltage under different gap widths, where X is the gap width. Please refer to the table below:
  • the width of the notch area is no greater than 0.4 microns. Further, the width of the notch area is 0.2-0.3 microns.
  • DIE die
  • the front-side structure of the FS IGBT includes a second conductivity type well region 112, an emitter region 114, an emitter electrode 116, and a trench gate structure (including a gate dielectric layer 124 and a gate electrode 122).
  • the trench gate structure extends down into drift region 20 .
  • the second conductivity type well region 112 is located on both sides of the trench gate structure and is located on the drift region 20 .
  • the emitter region 114 is located on both sides of the trench gate structure and in the second conductivity type well region 112 .
  • the emitter electrode 116 is located on the emitter region 114 and is electrically connected to the emitter region 114 .
  • the emitter electrode 116 is a metal electrode.
  • the trench gate structure includes a gate dielectric layer 124 located on the inner wall of the trench and a gate electrode 122 located in the trench and surrounded by the gate dielectric layer 124 .
  • the field stop insulated gate bipolar transistor also includes a gate 122 insulating dielectric layer 126 on.
  • the insulating dielectric layer 126 is an inter-layer dielectric (ILD) layer.
  • gate 122 is a polysilicon gate.
  • the collector region 322 is a P+ region
  • the field stop layer 312 is an N+ region
  • the emitter region 114 is an N+ region
  • the second conductivity type well region 112 is a P well
  • the drift region is an N- drift. district.
  • FIG. 3 is a flow chart of a manufacturing method of a field-stop insulated gate bipolar transistor according to an embodiment, including steps S310 to S340.
  • a wafer having a first conductivity type substrate is used, the first conductivity type substrate serves as the drift region 20 of the device, and an IGBT front side structure is formed on the front side of the wafer.
  • a trench can be etched on the substrate first, and then the inner wall of the trench can be repaired through sacrificial oxidation, and then a dense oxide layer can be grown as the gate dielectric layer 124, and then the trench can be filled with polysilicon and then returned to the trench.
  • the gate 122 is formed.
  • the second conductivity type well region 112 and the first conductivity type emitter region 114 are formed respectively through ion implantation.
  • the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type is N-type.
  • S320 Form an injection blocking structure on the back side of the drift region.
  • the back side of the drift region is the side opposite to the front structure of the IGBT.
  • the implant blocking structure is photoresist. Specifically, after the front-side structure of the IGBT is completed, the wafer can be turned over, and then photoresist is coated on the back of the wafer (the back of the wafer is facing up after flipping), and the photoresist is exposed using a photoresist. After development Photoresist 32 is formed as an implant blocking structure, see FIG. 4 . Note that the flipping of the wafer is not shown in Figure 4.
  • S330 form a collector region and a field stop layer on the back side of the drift region through an ion implantation process.
  • N-type ions and P-type ions are implanted respectively to form the field stop layer 312 and the collector region 322.
  • the collector region 322 has a second conductivity type and the field stop layer 312 has a first conductivity type. Ion implantation at the position of the implant blocking structure is blocked to form a gap region.
  • N-type ions may be implanted first, and then P-type ions may be implanted.
  • the backside implanted impurities may be activated by laser annealing.
  • the device structure after step S340 is completed can be seen in FIG. 1 .
  • the field stop layer 312 is located between the collector region 322 and the drift region 20 .
  • a gap 23 is formed in the collector region 322 and the field stop layer 312 on the back of the device by injecting a barrier structure.
  • the depletion region continues to extend at the gap 23, but is also affected by the gap 23.
  • the blocking effect of the field stop layer 312 on both sides prevents the gap area from penetrating, which not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thereby further improving the device withstand voltage.
  • the electrode layer 324 is a metal electrode serving as an electrode for the collector.
  • the width of the notch 23 is no greater than 0.4 microns, and accordingly the width of the photoresist 32 can be designed according to the width of the notch 23 .
  • the width of the notch 23 is 0.2-0.3 microns.
  • the present disclosure also provides another method for manufacturing a field-stop insulated gate bipolar transistor, which can prevent the photoresist 32 from falling off during the process if the width thereof is too small.
  • the manufacturing method of the field-stop insulated gate bipolar transistor of this embodiment includes steps S510 to S560.
  • a wafer having a first conductivity type substrate is used, the first conductivity type substrate serves as the drift region 20 of the device, and an IGBT front side structure is formed on the front side of the wafer.
  • a trench can be etched on the substrate first, and then the inner wall of the trench can be repaired through sacrificial oxidation, and then a dense oxide layer can be grown as the gate dielectric layer 124, and then the trench can be filled with polysilicon and then returned to the trench.
  • the gate 122 is formed.
  • the second conductivity type well region 112 and the first conductivity type emitter region 114 are formed respectively through ion implantation.
  • the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type is N-type.
  • the back side of the drift region is the side opposite to the front structure of the IGBT. Specifically, after the IGBT front-side structure is completed, the wafer can be turned over, and then photoresist is coated on the back of the wafer (the back of the wafer faces up after flipping), and the first photoresist is used to expose the photoresist. After development, the first photoresist layer 31 is formed.
  • the first photoresist layer 31 is used as an injection barrier layer, and N-type ions and P-type ions are implanted respectively to form a first field stop layer 312a and a first collector region 322a.
  • the first field stop layer 312a is located at the first between the current collection region 322a and the drift region 20.
  • the first collector region 322a has a second conductivity type, and the first field stop layer 312a has a first conductivity type. electrical type.
  • the photoresist is exposed using a second photoresist, and a second photoresist layer 33 is formed on the back side of the drift area after development.
  • S550 form a second collector region and a second field stop layer on the back side of the drift region through an ion implantation process.
  • the second photoresist layer 33 is used as an injection barrier layer, and N-type ions and P-type ions are implanted respectively to form a second field stop layer 312b and a second collector region 322b.
  • the second field stop layer 312b is located at the between the second collector region 322b and the drift region 20.
  • the second collector region 322b has a second conductivity type
  • the second field stop layer 312b has a first conductivity type.
  • the implantation in steps S530 and S550 is blocked, forming a gap 23 . Therefore, the positions and widths of the first photoresist layer 31 and the second photoresist layer 33 need to be designed according to the design position and design width of the notch 23 .
  • the backside implanted impurities may be activated by laser annealing.
  • the device structure after step S560 is completed can be seen in Figure 1.
  • a gap 23 is formed in the collector region and field stop layer on the back of the device.
  • the depletion region continues to extend at the gap 23, but is also affected by the field stop layers on both sides of the gap 23.
  • the blocking effect prevents the penetration of the notch area, which not only retains the structural characteristics of the FS IGBT, but is equivalent to increasing the thickness of the drift area, thereby further improving the device withstand voltage.
  • a gap 23 is formed in the overlapping area of the photoresist. The photoresist area formed twice is larger to avoid the photoresist area being too small and falling off, affecting the product yield.
  • the electrode layer 324 is a metal electrode serving as an electrode for the collector.
  • the width of notch 23 is no greater than 0.4 microns.
  • the width of the notch 23 is 0.2-0.3 microns.

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Abstract

本公开涉及一种场截止型绝缘栅双极晶体管及其制造方法，所述场截止型绝缘栅双极晶体管包括漂移区、正面结构及背面结构，所述背面结构包括：电极层；集电区，位于所述电极层上，具有第二导电类型；场截止层，位于所述集电区上，具有第一导电类型，所述漂移区位于所述场截止层上；其中，所述集电区和场截止层形成有缺口从而构成缺口区，所述缺口区具有第一导电类型，所述缺口区的掺杂浓度小于所述场截止层的掺杂浓度，所述漂移区具有第一导电类型。本公开能够进一步提高器件耐压。

Description

场截止型绝缘栅双极晶体管及其制造方法 技术领域
本公开涉及半导体制造领域，特别是涉及一种场截止型绝缘栅双极晶体管，还涉及一种场截止型绝缘栅双极晶体管的制造方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)作为双极型器件，综合了MOSFET(Metal Oxide Semiconductor Field Effect Transistor)的工作机理和双极型晶体管的工作机理，兼具两者的优点，是一种改良型的功率器件。较双极型晶体管而言，IGBT为电压控制型器件，并且大电流下增益高；较MOSFET而言，IGBT能够承受更高的电压，并且在大电流下导通压降低，功耗小。
按器件结构来分，IGBT在衬底上经历了PT(punch-through，穿通型)、NPT(non-punch-through非穿通型)及FS(field-stop，场截止型)三类结构。
对于纵向IGBT器件而言，正向阻断耐压是一项重要参数，业界希望在其他参数也能满足需求的前提下提高器件耐压。
发明内容
基于此，有必要提供一种能够提高器件耐压的场截止型绝缘栅双极晶体管及其制造方法。
一种场截止型绝缘栅双极晶体管，包括漂移区、正面结构及背面结构，所述背面结构包括：电极层；集电区，位于所述电极层上，具有第二导电类型；场截止层，位于所述集电区上，具有第一导电类型，所述漂移区位于所述场截止层上；其中，所述集电区和场截止层形成有缺口从而构成缺口区，所述缺口区具有第一导电类型，所述缺口区的掺杂浓度小于所述场截止层的掺杂浓度，所述漂移区具有第一导电类型；所述第一导电类型和第二导电类型为相反的导电类型。
上述场截止型绝缘栅双极晶体管，在器件背面的集电区和场截止层打开一个缺口，耗尽区在缺口处继续延展，但同时受到缺口两侧场截止层的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高 器件耐压。
在一些实施例中，所述缺口区为所述漂移区的一部分。
在一些实施例中，所述电极层是金属电极。
在一些实施例中，所述缺口区的宽度不大于0.4微米。
在一些实施例中，所述缺口区的宽度为0.2～0.3微米。
在一些实施例中，所述正面结构包括：沟槽栅结构，向下延伸至所述漂移区中；第二导电类型阱区，位于所述沟槽栅结构两侧；发射区，位于所述沟槽栅结构两侧、所述第二导电类型阱区中；发射极电极，位于所述发射区上并与所述发射区电性连接。
在一些实施例中，所述沟槽栅结构包括位于沟槽内壁的栅介质层，以及位于沟槽中且被所述栅介质层包围的栅极；所述场截止型绝缘栅双极晶体管还包括位于所述栅极上的绝缘介质层。
一种场截止型绝缘栅双极晶体管的制造方法，包括：
获取形成有漂移区和IGBT正面结构的晶圆；所述漂移区具有第一导电类型；在漂移区背面形成注入阻挡结构；所述漂移区背面为与所述IGBT正面结构相背的一面；通过离子注入工艺在所述漂移区背面形成集电区和场截止层，注入阻挡结构处的注入离子被阻挡从而形成缺口区；所述场截止层位于所述集电区和漂移区之间，所述集电区具有第二导电类型，所述场截止层具有第一导电类型；所述第一导电类型和第二导电类型为相反的导电类型；去除所述注入阻挡结构后，在所述晶圆的背面形成电极层。
上述场截止型绝缘栅双极晶体管的制造方法，在器件背面的集电区和场截止层打开一个缺口，耗尽区在缺口处继续延展，但同时受到缺口两侧场截止层的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高器件耐压。
在一些实施例中，所述缺口区的宽度不大于0.4微米。
在一些实施例中，所述缺口区的宽度为0.2～0.3微米。
一种场截止型绝缘栅双极晶体管的制造方法，包括：获取形成有漂移区和IGBT正面结构的晶圆；所述漂移区具有第一导电类型；通过光刻在漂移区背面形成第一光刻胶层；所述漂移区背面为与所述IGBT正面结构相背的一面；以所述第一光刻胶层为注入阻挡层，通过离子注入工艺在所述漂移区背面形成第一集电区和第一场截止层，所述第 一场截止层位于所述第一集电区和漂移区之间；去除所述第一光刻胶层后再次光刻，在所述漂移区背面形成第二光刻胶层，所述第二光刻胶层与所述第一光刻胶层形成的位置部分重叠；以所述第二光刻胶层为注入阻挡层，通过离子注入工艺在所述漂移区背面形成第二集电区和第二场截止层，所述第二场截止层位于所述第二集电区和漂移区之间；去除所述第二光刻胶层后，在所述晶圆的背面形成电极层；其中，所述第一集电区和第二集电区之间、所述第一场截止层和第二场截止层之间因离子注入被阻挡而形成缺口区；所述第一集电区和第二集电区具有第二导电类型，所述第一场截止层和第二场截止层具有第一导电类型；所述第一导电类型和第二导电类型为相反的导电类型。
上述场截止型绝缘栅双极晶体管的制造方法，在器件背面的集电区和场截止层打开一个缺口，耗尽区在缺口处继续延展，但同时受到缺口两侧场截止层的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高器件耐压。通过两次光刻+注入，在光刻胶重叠的区域形成该缺口，两次形成的光刻胶面积均较大，避免光刻胶面积太小而脱落影响产品良率。
在一些实施例中，所述缺口区的宽度不大于0.4微米。
在一些实施例中，所述缺口区的宽度为0.2～0.3微米。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中场截止型绝缘栅双极晶体管的剖面结构示意图；
图2是不同缺口宽度下器件耐压的仿真结果；
图3是一实施例中场截止型绝缘栅双极晶体管的制造方法的流程图；
图4是采用图3所示的方法制造IGBT的一实施例中步骤S320完成后器件结构的剖面示意图；
图5是另一实施例中场截止型绝缘栅双极晶体管的制造方法的流程图；
图6a是采用图5所示的方法制造IGBT的一实施例中步骤S530完成后器件结构的剖面示意图；
图6b是采用图5所示的方法制造IGBT的一实施例中步骤S550完成后器件结构的剖面示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、 整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述本公开的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区域的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时注入物所经过的表面之间的区域中的一些注入。因此，图中显示的区域实质上是示意性的，它们的形状并不意图显示器件的区域的实际形状且并不意图限定本公开的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
本公开提供一种高耐压的FS IGBT(Field-Stop Insulated Gate Bipolar Transistor)。图1是一实施例中场截止型绝缘栅双极晶体管的剖面结构示意图，包括正面结构、背面结构及第一导电类型的漂移区20。其中背面结构包括场截止层312、集电区322以及电极层324(作为集电极的电极)。集电区322位于电极层324上，具有第二导电类型。场截止层312位于集电区322上，具有第一导电类型。漂移区20位于场截止层312上。集电区322和场截止层312形成有缺口23从而构成缺口区，缺口区具有第一导电类型，且缺口区的掺杂浓度小于场截止层312的掺杂浓度。在图1所示的实施例中，第一导电类型为N型，第二导电类型为P型；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
上述场截止型绝缘栅双极晶体管，在器件背面的集电区322和场截止层312打开一个缺口23，耗尽区在缺口23处继续延展，但同时受到缺口23两侧场截止层312的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高器件耐压。
在本公开的一个实施例中，缺口区为漂移区20的一部分。整个漂移区20的掺杂浓度可以不是完全相同的。在图1所示的实施例中，缺口23与电极层324直接接触。在 其他实施例中，缺口23也可以不是完全贯穿集电区322，即在缺口23的底部还留有一定厚度的集电区322，缺口23与电极层324之间被残留的集电区322隔开。换言之，缺口区贯穿场截止层312，至少贯穿部分集电区322。
在本公开的一个实施例中，电极层324为金属电极。
缺口23如果过大，反而会降低器件耐压。图2是不同缺口宽度下器件耐压的仿真结果，其中X为所述缺口宽度。请一并参照下表：
表1
可以看到缺口23的宽度X如果过大，则器件耐压反而会比没有缺口(X＝0)时更低，例如X＝0.5时耐压就比X＝0时更低。在本公开的一个实施例中，缺口区的宽度不大于0.4微米。进一步地，缺口区的宽度为0.2～0.3微米。实际制造时，一个管芯(DIE)中可以有多个IGBT原胞，每个IGBT原胞可以设置一个或两个以上的缺口23。
在图1所示的实施例中，FS IGBT的正面结构包括第二导电类型阱区112、发射区114、发射极电极116及沟槽栅结构(包括栅介质层124和栅极122)。沟槽栅结构向下延伸至漂移区20中。第二导电类型阱区112位于沟槽栅结构两侧，并且位于漂移区20上。发射区114位于沟槽栅结构两侧、第二导电类型阱区112中。发射极电极116位于发射区114上并与发射区114电性连接。发射极电极116为金属电极。
在图1所示的实施例中，沟槽栅结构包括位于沟槽内壁的栅介质层124及位于沟槽中且被栅介质层124包围的栅极122。场截止型绝缘栅双极晶体管还包括位于栅极122 上的绝缘介质层126。在本公开的一个实施例中，绝缘介质层126是层间介质(Inter-Layer Dielectric，ILD)层。在本公开的一个实施例中，栅极122为多晶硅栅极。
在图1所示的实施例中，集电区322为P+区，场截止层312为N+区，发射区114为N+区，第二导电类型阱区112为P阱，漂移区为N-漂移区。
本公开相应提供一种场截止型绝缘栅双极晶体管的制造方法。图3是一实施例中场截止型绝缘栅双极晶体管的制造方法的流程图，包括步骤S310到S340。
S310，获取形成有漂移区和IGBT正面结构的晶圆。
在本公开的一个实施例中，采用具有第一导电类型衬底的晶圆，第一导电类型衬底作为器件的漂移区20，并在晶圆正面形成IGBT正面结构。具体地，可以先在衬底上刻蚀出沟槽，然后通过牺牲氧化对沟槽的内壁进行修复，接着生长一层致密的氧化层作为栅介质层124，再向沟槽内填充多晶硅后回刻，形成栅极122。之后分别通过离子注入形成第二导电类型阱区112和第一导电类型的发射区114。再于栅极122上形成绝缘介质层126，最后打孔填入金属形成发射极电极116来引出发射极。在本公开的一个实施例中，第一导电类型为N型，第二导电类型为P型；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
S320，在漂移区背面形成注入阻挡结构。
漂移区背面即与IGBT正面结构相背的一面。在本公开的一个实施例中，注入阻挡结构为光刻胶。具体地，可以在IGBT正面结构做完后，翻转晶圆，然后在晶圆背面(翻转后晶圆背面朝上)涂覆光刻胶，使用光刻版对光刻胶进行曝光，在显影后形成光刻胶32，作为注入阻挡结构，参见图4。注意图4中未表示出晶圆的翻转。
S330，通过离子注入工艺在漂移区背面形成集电区和场截止层。
分别注入N型离子和P型离子，形成场截止层312和集电区322。集电区322具有第二导电类型，场截止层312具有第一导电类型。注入阻挡结构位置处的离子注入被阻挡从而形成缺口区。在本公开的一个实施例中，可以先注入N型离子，再注入P型离子。
S340，去除注入阻挡结构后在晶圆的背面形成电极层。
在本公开的一个实施例中，形成电极层324之前，可以先通过激光退火激活背面注入杂质。步骤S340完成后的器件结构可以参见图1，场截止层312位于集电区322和漂移区20之间。
上述场截止型绝缘栅双极晶体管的制造方法，通过注入阻挡结构在器件背面的集电区322和场截止层312形成一个缺口23，耗尽区在缺口23处继续延展，但同时受到缺口23两侧场截止层312的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高器件耐压。
在本公开的一个实施例中，电极层324是金属电极，作为集电极的电极。
在本公开的一个实施例中，缺口23的宽度不大于0.4微米，相应地可以根据缺口23的宽度来设计光刻胶32的宽度。
在本公开的一个实施例中，缺口23的宽度为0.2～0.3微米。
本公开还提供另一种场截止型绝缘栅双极晶体管的制造方法，能够避免光刻胶32的宽度过小导致在工艺过程中脱落。参见图5，该实施例的场截止型绝缘栅双极晶体管的制造方法包括步骤S510到S560。
S510，获取形成有漂移区和IGBT正面结构的晶圆。
在本公开的一个实施例中，采用具有第一导电类型衬底的晶圆，第一导电类型衬底作为器件的漂移区20，并在晶圆正面形成IGBT正面结构。具体地，可以先在衬底上刻蚀出沟槽，然后通过牺牲氧化对沟槽的内壁进行修复，接着生长一层致密的氧化层作为栅介质层124，再向沟槽内填充多晶硅后回刻，形成栅极122。之后分别通过离子注入形成第二导电类型阱区112和第一导电类型的发射区114。再于栅极122上形成绝缘介质层126，最后打孔填入金属形成发射极电极116来引出发射极。在本公开的一个实施例中，第一导电类型为N型，第二导电类型为P型；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
S520，通过光刻在漂移区背面形成第一光刻胶层。
漂移区背面即与IGBT正面结构相背的一面。具体地，可以在IGBT正面结构做完后，翻转晶圆，然后在晶圆背面(翻转后晶圆背面朝上)涂覆光刻胶，使用第一光刻版对光刻胶进行曝光，在显影后形成第一光刻胶层31。
S530，通过离子注入工艺在漂移区背面形成第一集电区和第一场截止层。
参照图6a，以第一光刻胶层31为注入阻挡层，分别注入N型离子和P型离子，形成第一场截止层312a和第一集电区322a，第一场截止层312a位于第一集电区322a和漂移区20之间。第一集电区322a具有第二导电类型，第一场截止层312a具有第一导 电类型。
S540，去胶后再次光刻形成与第一光刻胶层形成的位置部分重叠的第二光刻胶层。
使用第二光刻版对光刻胶进行曝光，显影后在漂移区背面形成第二光刻胶层33。
S550，通过离子注入工艺在漂移区背面形成第二集电区和第二场截止层。
参照图6b，以第二光刻胶层33为注入阻挡层，分别注入N型离子和P型离子，形成第二场截止层312b和第二集电区322b，第二场截止层312b位于第二集电区322b和漂移区20之间。第二集电区322b具有第二导电类型，第二场截止层312b具有第一导电类型。在第一光刻胶层31与第二光刻胶层33重叠的位置，步骤S530和步骤S550的注入均被阻挡，形成缺口23。因此需要根据缺口23的设计位置和设计宽度来设计第一光刻胶层31与第二光刻胶层33的位置与宽度。
S560，去胶后在晶圆的背面形成电极层。
在本公开的一个实施例中，形成电极层324之前，可以先通过激光退火激活背面注入杂质。步骤S560完成后的器件结构可以参见图1。
上述场截止型绝缘栅双极晶体管的制造方法，在器件背面的集电区和场截止层形成一个缺口23，耗尽区在缺口23处继续延展，但同时受到缺口23两侧场截止层的阻挡作用，不至于穿通缺口区，既保留了FS IGBT的结构特性，又等效于增加了漂移区厚度，从而能够进一步提高器件耐压。通过两次光刻+注入，在光刻胶重叠的区域形成缺口23，两次形成的光刻胶面积均较大，避免光刻胶面积太小而脱落影响产品良率。
在本公开的一个实施例中，电极层324是金属电极，作为集电极的电极。
在本公开的一个实施例中，缺口23的宽度不大于0.4微米。
在本公开的一个实施例中，缺口23的宽度为0.2～0.3微米。
应该理解的是，虽然本公开的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且本公开的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种场截止型绝缘栅双极晶体管，包括漂移区、正面结构及背面结构，其特征在于，所述背面结构包括：
    电极层；
    集电区，位于所述电极层上，具有第二导电类型；
    场截止层，位于所述集电区上，具有第一导电类型，所述漂移区位于所述场截止层上；
    缺口区，其中，所述缺口区贯穿所述场截止层，且至少贯穿部分所述集电区，所述缺口区具有第一导电类型，所述缺口区的掺杂浓度小于所述场截止层的掺杂浓度，所述漂移区具有第一导电类型；所述第一导电类型和第二导电类型为相反的导电类型。
  2. 根据权利要求1所述的场截止型绝缘栅双极晶体管，其特征在于，所述缺口区为所述漂移区的一部分。
  3. 根据权利要求1所述的场截止型绝缘栅双极晶体管，其特征在于，所述电极层是金属电极。
  4. 根据权利要求1所述的场截止型绝缘栅双极晶体管，其特征在于，所述缺口区的宽度不大于0.4微米。
  5. 根据权利要求4所述的场截止型绝缘栅双极晶体管，其特征在于，所述缺口区的宽度为0.2～0.3微米。
  6. 根据权利要求1所述的场截止型绝缘栅双极晶体管，其特征在于，所述正面结构包括：
    沟槽栅结构，向下延伸至所述漂移区中；
    第二导电类型阱区，位于所述沟槽栅结构两侧；
    发射区，位于所述沟槽栅结构两侧、所述第二导电类型阱区中；
    发射极电极，位于所述发射区上并与所述发射区电性连接。
  7. 根据权利要求6所述的场截止型绝缘栅双极晶体管，其特征在于，所述沟槽栅结构包括位于沟槽内壁的栅介质层，以及位于沟槽中且被所述栅介质层包围的栅极；
    所述场截止型绝缘栅双极晶体管还包括位于所述栅极上的绝缘介质层。
  8. 一种场截止型绝缘栅双极晶体管的制造方法，包括：
    获取形成有漂移区和IGBT正面结构的晶圆；所述漂移区具有第一导电类型；
    在漂移区背面形成注入阻挡结构；所述漂移区背面为与所述IGBT正面结构相背的一面；
    通过离子注入工艺在所述漂移区背面形成集电区和场截止层，所述注入阻挡结构处的注入离子被阻挡从而形成缺口区；所述场截止层位于所述集电区和所述漂移区之间，所述集电区具有第二导电类型，所述场截止层具有第一导电类型；所述第一导电类型和所述第二导电类型为相反的导电类型；
    去除所述注入阻挡结构后，在所述晶圆的背面形成电极层。
  9. 根据权利要求8所述的场截止型绝缘栅双极晶体管的制造方法，其特征在于，所述缺口区的宽度不大于0.4微米。
  10. 根据权利要求8所述的场截止型绝缘栅双极晶体管的制造方法，其特征在于，所述缺口区的宽度为0.2～0.3微米。
  11. 一种场截止型绝缘栅双极晶体管的制造方法，包括：
    获取形成有漂移区和IGBT正面结构的晶圆；所述漂移区具有第一导电类型；
    通过光刻在漂移区背面形成第一光刻胶层；所述漂移区背面为与所述IGBT正面结构相背的一面；
    以所述第一光刻胶层为注入阻挡层，通过离子注入工艺在所述漂移区背面形成第一集电区和第一场截止层，所述第一场截止层位于所述第一集电区和漂移区之间；
    去除所述第一光刻胶层后再次光刻，在所述漂移区背面形成第二光刻胶层，所述第二光刻胶层与所述第一光刻胶层形成的位置部分重叠；
    以所述第二光刻胶层为注入阻挡层，通过离子注入工艺在所述漂移区背面形成第二集电区和第二场截止层，所述第二场截止层位于所述第二集电区和所述漂移区之间；
    去除所述第二光刻胶层后，在所述晶圆的背面形成电极层；
    其中，所述第一集电区和第二集电区之间、所述第一场截止层和所述第二场截止层之间因离子注入被阻挡而形成缺口区；所述第一集电区和所述第二集电区具有第二导电类型，所述第一场截止层和所述第二场截止层具有第一导电类型；所述第一导电类型和所述第二导电类型为相反的导电类型。
  12. 根据权利要求11所述的场截止型绝缘栅双极晶体管的制造方法，其特征在于，所述缺口区的宽度不大于0.4微米。
  13. 根据权利要求11所述的场截止型绝缘栅双极晶体管的制造方法，其特征在于，所述缺口区的宽度为0.2～0.3微米。
PCT/CN2023/101143 2022-08-04 2023-06-19 场截止型绝缘栅双极晶体管及其制造方法 WO2024027357A1 (zh)

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